Detail publikace

Ultra-Low Voltage CMOS Current-Mode Four-Quadrant Multiplier

Originální název

Ultra-Low Voltage CMOS Current-Mode Four-Quadrant Multiplier

Anglický název

Ultra-Low Voltage CMOS Current-Mode Four-Quadrant Multiplier

Jazyk

en

Originální abstrakt

A novel configuration of a four-quadrant current multiplier is introduced in this paper. The realization is achieved through the utilization of the voltage translinear principle; the derived topology simultaneously offers the attractive benefits of ultra-low voltage operation and reduced dc power dissipation, in comparison with the corresponding already published multipliers. The above have been achieved without increasing the circuit complexity. The behavior of the multiplier has been evaluated through simulation results, using the Analog Design Environment and the design kit provided by the TSMC 180nm CMOS process.

Anglický abstrakt

A novel configuration of a four-quadrant current multiplier is introduced in this paper. The realization is achieved through the utilization of the voltage translinear principle; the derived topology simultaneously offers the attractive benefits of ultra-low voltage operation and reduced dc power dissipation, in comparison with the corresponding already published multipliers. The above have been achieved without increasing the circuit complexity. The behavior of the multiplier has been evaluated through simulation results, using the Analog Design Environment and the design kit provided by the TSMC 180nm CMOS process.

BibTex


@article{BUT105548,
  author="Andreas-Christos {Demartinos} and Costas {Psychalinos} and Fabian {Khateb}",
  title="Ultra-Low Voltage CMOS Current-Mode Four-Quadrant Multiplier",
  annote="A novel configuration of a four-quadrant current multiplier is introduced in this paper. The realization is achieved through the utilization of the voltage translinear principle; the derived topology simultaneously offers the attractive benefits of ultra-low voltage operation and reduced dc power dissipation, in comparison with the corresponding already published multipliers. The above have been achieved without increasing the circuit complexity. The behavior of the multiplier has been evaluated through simulation results, using the Analog Design Environment and the design kit provided by the TSMC 180nm CMOS process.",
  address="Taylor & Francis",
  chapter="105548",
  doi="10.1080/21681724.2014.900824",
  institution="Taylor & Francis",
  number="4",
  volume="2014 (2)",
  year="2014",
  month="february",
  pages="224--233",
  publisher="Taylor & Francis",
  type="journal article in Scopus"
}