Detail publikace

Low-Latency Modular Packet Header Parser for FPGA

Originální název

Low-Latency Modular Packet Header Parser for FPGA

Anglický název

Low-Latency Modular Packet Header Parser for FPGA

Jazyk

en

Originální abstrakt

Packet parsing is the basic operation performed at all points of the network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules, however the high-speed parsers often use very large chip area. We propose novel architecture of pipelined packet parser, which in addition to high throughput (over 100 Gb/s) offers also low latency. Moreover, the latency to throughput ratio can be finely tuned to fit the particular application. The parser is handoptimized thanks to the direct implementation in VHDL, yet the structure is very uniform and easily extensible for new protocols.

Anglický abstrakt

Packet parsing is the basic operation performed at all points of the network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules, however the high-speed parsers often use very large chip area. We propose novel architecture of pipelined packet parser, which in addition to high throughput (over 100 Gb/s) offers also low latency. Moreover, the latency to throughput ratio can be finely tuned to fit the particular application. The parser is handoptimized thanks to the direct implementation in VHDL, yet the structure is very uniform and easily extensible for new protocols.

BibTex


@inproceedings{BUT97063,
  author="Lukáš {Kekely} and Viktor {Puš} and Jan {Kořenek}",
  title="Low-Latency Modular Packet Header Parser for FPGA",
  annote="Packet parsing is the basic operation performed at all points of the network
infrastructure. Modern networks impose challenging requirements on the
performance and configurability of packet parsing modules, however the high-speed
parsers often use very large chip area. We propose novel architecture of
pipelined packet parser, which in addition to high throughput (over 100 Gb/s)
offers also low latency. Moreover, the latency to throughput ratio can be finely
tuned to fit the particular application. The parser is handoptimized thanks to
the direct implementation in VHDL, yet the structure is very uniform and easily
extensible for new protocols.",
  address="Association for Computing Machinery",
  booktitle="ACM/IEEE Symposium on Architectures for Networking and Communications Systems",
  chapter="97063",
  edition="NEUVEDEN",
  howpublished="print",
  institution="Association for Computing Machinery",
  year="2012",
  month="november",
  pages="77--78",
  publisher="Association for Computing Machinery",
  type="conference paper"
}