Detail publikace

Reduction of Test Vectors Number based on Parasitic Capacity Extraction of Scan Chain Wires

Originální název

Reduction of Test Vectors Number based on Parasitic Capacity Extraction of Scan Chain Wires

Anglický název

Reduction of Test Vectors Number based on Parasitic Capacity Extraction of Scan Chain Wires

Jazyk

en

Originální abstrakt

In this paper, method for scan chain optimisation performed after physical layout is presented. It is shown how the method can be used to decrease the number of test vectors. The principles of the method are based on parasitic capacity extraction, eliminating some bridging faults in the physical layout and subsequent reduction of the number of test vectors needed to test the circuit. The method was verified on circuits from benchmark set, experimental results are provided and discussed. It is expected that the method can be used in mass production of electronic components.

Anglický abstrakt

In this paper, method for scan chain optimisation performed after physical layout is presented. It is shown how the method can be used to decrease the number of test vectors. The principles of the method are based on parasitic capacity extraction, eliminating some bridging faults in the physical layout and subsequent reduction of the number of test vectors needed to test the circuit. The method was verified on circuits from benchmark set, experimental results are provided and discussed. It is expected that the method can be used in mass production of electronic components.

BibTex


@inproceedings{BUT96976,
  author="Pavel {Bartoš} and Zdeněk {Kotásek}",
  title="Reduction of Test Vectors Number based on Parasitic Capacity Extraction of Scan Chain Wires",
  annote="In this paper, method for scan chain optimisation performed after physical layout
is presented. It is shown how the method can be used to decrease the number of
test vectors. The principles of the method are based on parasitic capacity
extraction, eliminating some bridging faults in the physical layout and
subsequent reduction of the number of test vectors needed to test the circuit.
The method was verified on circuits from benchmark set, experimental results are
provided and discussed. It is expected that the method can be used in mass
production of electronic components.",
  address="Faculty of Electrical Engineering and Informatics, University of Technology Košice",
  booktitle="Proceedings of CSE 2012 International Scientific Conference on Computer Science and Engineering",
  chapter="96976",
  edition="NEUVEDEN",
  howpublished="print",
  institution="Faculty of Electrical Engineering and Informatics, University of Technology Košice",
  year="2012",
  month="october",
  pages="162--169",
  publisher="Faculty of Electrical Engineering and Informatics, University of Technology Košice",
  type="conference paper"
}