Detail publikace

On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming

Originální název

On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming

Anglický název

On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming

Jazyk

en

Originální abstrakt

The paper deals with the evolutionary post synthesis optimization of complex combinational circuits with the aim of reducing the area on a chip as much as possible. In order to optimize complex circuits, Cartesian Genetic Programming (CGP) is employed where the fitness function is based on a formal equivalence checking algorithm rather than evaluating all possible input assignments. The standard selection strategy of CGP is modified to be more explorative and so agile in very rugged fitness landscapes. It was shown on the LGSynth93 benchmark circuits that the modified selection strategy leads to more compact circuits in roughly 50% cases. The average area improvement is 24% with respect to the results of conventional synthesis. Delay of optimized circuits was also analyzed. 

Anglický abstrakt

The paper deals with the evolutionary post synthesis optimization of complex combinational circuits with the aim of reducing the area on a chip as much as possible. In order to optimize complex circuits, Cartesian Genetic Programming (CGP) is employed where the fitness function is based on a formal equivalence checking algorithm rather than evaluating all possible input assignments. The standard selection strategy of CGP is modified to be more explorative and so agile in very rugged fitness landscapes. It was shown on the LGSynth93 benchmark circuits that the modified selection strategy leads to more compact circuits in roughly 50% cases. The average area improvement is 24% with respect to the results of conventional synthesis. Delay of optimized circuits was also analyzed. 

BibTex


@inproceedings{BUT96926,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming",
  annote="

The paper deals with the evolutionary post synthesis optimization of complex
combinational circuits with the aim of reducing the area on a chip as much as
possible. In order to optimize complex circuits, Cartesian Genetic Programming
(CGP) is employed where the fitness function is based on a formal equivalence
checking algorithm rather than evaluating all possible input assignments. The
standard selection strategy of CGP is modified to be more explorative and so
agile in very rugged fitness landscapes. It was shown on the LGSynth93 benchmark
circuits that the modified selection strategy leads to more compact circuits in
roughly 50% cases. The average area improvement is 24% with respect to the
results of conventional synthesis. Delay of optimized circuits was also
analyzed. ",
  address="Institute of Electrical and Electronics Engineers",
  booktitle="2012 IEEE World Congress on Computational Intelligence",
  chapter="96926",
  doi="10.1109/CEC.2012.6256649",
  edition="NEUVEDEN",
  howpublished="electronic, physical medium",
  institution="Institute of Electrical and Electronics Engineers",
  year="2012",
  month="june",
  pages="2379--2386",
  publisher="Institute of Electrical and Electronics Engineers",
  type="conference paper"
}