Detail publikace

NETWORK CONNECTION FPGA DEVICES

ŠTRAUS, P.

Originální název

NETWORK CONNECTION FPGA DEVICES

Český název

NETWORK CONNECTION FPGA DEVICES

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

cs

Originální abstrakt

This paper deals with a design of the network connection between two development boards ML505 and FPGA devices Virtex-5. FPGA devices are programmed in VHDL (VHSIC hardware description language) language in ISE Xilinx software. Data are sent in the UDP (User Datagram Protocol) datagrams. In the first step, UDP datagrams are sent to the PC (personal computer), where the UDP datagrams are received and checked in the Wireshark programme. After successful connection of FPGA with PC, there are two FPGA devices connected together. An alphabetic character from the LCD display is transferred in the data payload of the UDP datagram.

Český abstrakt

This paper deals with a design of the network connection between two development boards ML505 and FPGA devices Virtex-5. FPGA devices are programmed in VHDL (VHSIC hardware description language) language in ISE Xilinx software. Data are sent in the UDP (User Datagram Protocol) datagrams. In the first step, UDP datagrams are sent to the PC (personal computer), where the UDP datagrams are received and checked in the Wireshark programme. After successful connection of FPGA with PC, there are two FPGA devices connected together. An alphabetic character from the LCD display is transferred in the data payload of the UDP datagram.

Klíčová slova

Network connection, FPGA, VHDL, UDP datagrams, Xilinx ISE

Rok RIV

2012

Vydáno

26.04.2012

Nakladatel

LITERA Brno

Místo

Brno, ČR

ISBN

978-80-214-4462-1

Kniha

STUDENT EEICT Proceedings of the 18th Conference volume 3

Číslo edice

první

Strany od

44

Strany do

48

Strany počet

5

BibTex


@inproceedings{BUT92200,
  author="Pavel {Štraus}",
  title="NETWORK CONNECTION FPGA DEVICES",
  annote="This paper deals with a design of the network connection between two development
boards ML505 and FPGA devices Virtex-5. FPGA devices are programmed in VHDL (VHSIC
hardware description language) language in ISE Xilinx software. Data are sent in the UDP (User
Datagram Protocol) datagrams. In the first step, UDP datagrams are sent to the PC (personal computer),
where the UDP datagrams are received and checked in the Wireshark programme. After
successful connection of FPGA with PC, there are two FPGA devices connected together. An alphabetic
character from the LCD display is transferred in the data payload of the UDP datagram.",
  address="LITERA Brno",
  booktitle="STUDENT EEICT Proceedings of the 18th Conference volume 3",
  chapter="92200",
  howpublished="print",
  institution="LITERA Brno",
  year="2012",
  month="april",
  pages="44--48",
  publisher="LITERA Brno",
  type="conference paper"
}