Detail publikace

Fault Tolerant System Design and SEU Injection based Testing

Originální název

Fault Tolerant System Design and SEU Injection based Testing

Anglický název

Fault Tolerant System Design and SEU Injection based Testing

Jazyk

en

Originální abstrakt

The methodology for design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into SRAM-based FPGA. The methodology includes detection and localization of a faulty module in the system and its repair and bringing the system back to the state in which it operates correctly. The automatic repair process of a faulty module is implemented by a partial dynamic reconfiguration driven by a generic controller inside FPGA. The presented methodology was verified on the ML506 development board with Virtex5 FPGA for different types of RTL components. Fault tolerant systems developed by the presented methodology were tested by means of the newly developed SEU simulation framework. The framework is based on the SEU simulation through the JTAG interface and allows us to select the region of the FPGA where the SEU is placed. The simulator does not require any changes in the tested design and is fully independent of the functions in the FPGA. The external SEU generator into FPGA is implemented and its function is verified on an evaluation board ML506 for several types of fault tolerant architectures. The experimental results show the fault coverage and SEU occurrence causing faulty behavior of verified architectures.

Anglický abstrakt

The methodology for design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into SRAM-based FPGA. The methodology includes detection and localization of a faulty module in the system and its repair and bringing the system back to the state in which it operates correctly. The automatic repair process of a faulty module is implemented by a partial dynamic reconfiguration driven by a generic controller inside FPGA. The presented methodology was verified on the ML506 development board with Virtex5 FPGA for different types of RTL components. Fault tolerant systems developed by the presented methodology were tested by means of the newly developed SEU simulation framework. The framework is based on the SEU simulation through the JTAG interface and allows us to select the region of the FPGA where the SEU is placed. The simulator does not require any changes in the tested design and is fully independent of the functions in the FPGA. The external SEU generator into FPGA is implemented and its function is verified on an evaluation board ML506 for several types of fault tolerant architectures. The experimental results show the fault coverage and SEU occurrence causing faulty behavior of verified architectures.

BibTex


@article{BUT91471,
  author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek} and Lukáš {Mičulka}",
  title="Fault Tolerant System Design and SEU Injection based Testing",
  annote="The methodology for design and testing of fault tolerant systems implemented into
an FPGA platform with different types of diagnostic techniques is presented in
this paper. Basic principles of partial dynamic reconfiguration are described
together with their impact on the fault tolerance features of the digital design
implemented into SRAM-based FPGA. The methodology includes detection and
localization of a faulty module in the system and its repair and bringing the
system back to the state in which it operates correctly. The automatic repair
process of a faulty module is implemented by a partial dynamic reconfiguration
driven by a generic controller inside FPGA. The presented methodology was
verified on the ML506 development board with Virtex5 FPGA for different types of
RTL components. Fault tolerant systems developed by the presented methodology
were tested by means of the newly developed SEU simulation framework. The
framework is based on the SEU simulation through the JTAG interface and allows us
to select the region of the FPGA where the SEU is placed. The simulator does not
require any changes in the tested design and is fully independent of the
functions in the FPGA. The external SEU generator into FPGA is implemented and
its function is verified on an evaluation board ML506 for several types of fault
tolerant architectures. The experimental results show the fault coverage and SEU
occurrence causing faulty behavior of verified architectures.",
  address="NEUVEDEN",
  booktitle="Microprocessors and Microsystems Journal SI: Digital System Safety and Security",
  chapter="91471",
  edition="NEUVEDEN",
  howpublished="online",
  institution="NEUVEDEN",
  number="37",
  volume="2013",
  year="2013",
  month="february",
  pages="155--173",
  publisher="NEUVEDEN",
  type="journal article - other"
}