Detail publikace

Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems

Originální název

Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems

Anglický název

Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems

Jazyk

en

Originální abstrakt

In the paper, a concept and an early analysis of an embedded hardware/software architecture designed to prevent the software from both timing disturbances and interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the hardware (software) part of an embedded application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt interrupt service rates to the actual software load being monitored with no intrusion to the software. According to the actual software load it is able to buffer all interrupts and related data while the software is highly loaded and redirect the interrupts to the MCU as soon as the software becomes underloaded.

Anglický abstrakt

In the paper, a concept and an early analysis of an embedded hardware/software architecture designed to prevent the software from both timing disturbances and interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the hardware (software) part of an embedded application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt interrupt service rates to the actual software load being monitored with no intrusion to the software. According to the actual software load it is able to buffer all interrupts and related data while the software is highly loaded and redirect the interrupts to the MCU as soon as the software becomes underloaded.

BibTex


@inproceedings{BUT91462,
  author="Josef {Strnadel}",
  title="Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems",
  annote="In the paper, a concept and an early analysis of an embedded hardware/software
architecture designed to prevent the software from both timing disturbances and
interrupt overloads is outlined. The architecture is composed of an FPGA (MCU)
used to run the hardware (software) part of an embedded application. Comparing to
previous approaches, novelty of the architecture can be seen in the fact it is
able to adapt interrupt service rates to the actual software load being monitored
with no intrusion to the software. According to the actual software load it is
able to buffer all interrupts and related data while the software is highly
loaded and redirect the interrupts to the MCU as soon as the software becomes
underloaded.",
  address="IEEE Computer Society",
  booktitle="Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)",
  chapter="91462",
  doi="10.1109/DDECS.2012.6219037",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2012",
  month="april",
  pages="121--126",
  publisher="IEEE Computer Society",
  type="conference paper"
}