Detail publikace

Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity

KOŠAŘ, V. KOŘENEK, J.

Originální název

Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity

Anglický název

Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity

Jazyk

en

Originální abstrakt

Intrusion Detection Systems have to match large sets of regular expressions to detect malicious traffic on multi-gigabit networks. Many algorithms and architectures have been proposed to accelerate pattern matching, but formal methods for reduction of Nondeterministic finite automata have not been used yet. We propose to use reduction of automata by similarity to match larger set of regular expressions in FPGA. Proposed reduction is able to decrease the number of states by more than 32% and the amount of transitions by more than 31%. The amount of look-up tables is reduced by more than 15% and the amount of flip-flops by more than 34%.

Anglický abstrakt

Intrusion Detection Systems have to match large sets of regular expressions to detect malicious traffic on multi-gigabit networks. Many algorithms and architectures have been proposed to accelerate pattern matching, but formal methods for reduction of Nondeterministic finite automata have not been used yet. We propose to use reduction of automata by similarity to match larger set of regular expressions in FPGA. Proposed reduction is able to decrease the number of states by more than 32% and the amount of transitions by more than 31%. The amount of look-up tables is reduced by more than 15% and the amount of flip-flops by more than 34%.

Dokumenty

BibTex


@inproceedings{BUT76456,
  author="Vlastimil {Košař} and Jan {Kořenek}",
  title="Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity",
  annote="Intrusion Detection Systems have to match large sets of regular expressions to
detect malicious traffic on multi-gigabit networks. Many algorithms and
architectures have been proposed to accelerate pattern matching, but formal
methods for reduction of Nondeterministic finite automata have not been used yet.
We propose to use reduction of automata by similarity to match larger set of
regular expressions in FPGA. Proposed reduction is able to decrease the number of
states by more than 32% and the amount of transitions by more than 31%. The
amount of look-up tables is reduced by more than 15% and the amount of flip-flops
by more than 34%.",
  address="IEEE Computer Society",
  booktitle="IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011",
  chapter="76456",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2011",
  month="april",
  pages="401--402",
  publisher="IEEE Computer Society",
  type="conference paper"
}