Detail publikace

Hardware Accelerated Functional Verification

ZACHARIÁŠOVÁ, M.

Originální název

Hardware Accelerated Functional Verification

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

Functional verification is a widespread technique for checking whether a hardware system satisfies a given correctness specification. The complexity of modern computer systems is rapidly rising and the verification process takes significant amount of time. It is a challenging process to find appropriate acceleration techniques. We introduce a strategy for acceleration of functional verification using FPGAs by targeting special components of the verification environment to the FPGA.

Klíčová slova

functional verification, testbench, SystemVerilog, hardware acceleration, FPGA

Autoři

ZACHARIÁŠOVÁ, M.

Rok RIV

2011

Vydáno

4. 7. 2011

Nakladatel

Faculty of Information Technology BUT

Místo

Brno

ISBN

978-80-214-4272-6

Kniha

Proceedings of the 17th Conference STUDENT EEICT 2011

Strany od

321

Strany do

323

Strany počet

3

URL

http://www.feec.vutbr.cz/EEICT/2011/sbornik/02-Magisterske%20projekty/10-Pocitacove%20systemy/10-xsimko03.pdf

BibTex

@inproceedings{BUT76419,
  author="Marcela {Zachariášová}",
  title="Hardware Accelerated Functional Verification",
  booktitle="Proceedings of the 17th Conference STUDENT EEICT 2011",
  year="2011",
  pages="321--323",
  publisher="Faculty of Information Technology BUT",
  address="Brno",
  isbn="978-80-214-4272-6",
  url="http://www.feec.vutbr.cz/EEICT/2011/sbornik/02-Magisterske%20projekty/10-Pocitacove%20systemy/10-xsimko03.pdf"
}