Detail publikace

Hardware Architecture for Packet Classification with Prefix Coloring

PUŠ, V. KAJAN, M. KOŘENEK, J.

Originální název

Hardware Architecture for Packet Classification with Prefix Coloring

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

Packet classification is a widely used operation in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays algorithms implemented in hardware can achieve multigigabit speeds, but suffer with great memory overhead. We propose a new algorithm and hardware architecture which reduces memory requirements of decomposition based methods for packet classification. The algorithm uses prefix coloring to reduce large amount of Cartesian product rules at the cost of an additional pipelined processing and a few bits added into results of the longest prefix match operation. The proposed hardware architecture is designed as a processing pipeline with the throughput of 266 million packets per second using commodity FPGA and one external memory. The greatest strength of the algorithm is the constant time complexity of the search operation, which makes the solution resistant to various classes of network security attacks.

Klíčová slova

FPGA, SRAM, hardware, parallelism, classification

Autoři

PUŠ, V.; KAJAN, M.; KOŘENEK, J.

Rok RIV

2011

Vydáno

13. 4. 2011

Nakladatel

IEEE Computer Society

Místo

Cottbus

ISBN

978-1-4244-9753-9

Kniha

IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011

Strany od

231

Strany do

236

Strany počet

6

URL

BibTex

@inproceedings{BUT76313,
  author="Viktor {Puš} and Michal {Kajan} and Jan {Kořenek}",
  title="Hardware Architecture for Packet Classification with Prefix Coloring",
  booktitle="IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011",
  year="2011",
  pages="231--236",
  publisher="IEEE Computer Society",
  address="Cottbus",
  isbn="978-1-4244-9753-9",
  url="https://www.fit.vut.cz/research/publication/9564/"
}