Detail publikace

On the cascade realization of sparse logic functions

Originální název

On the cascade realization of sparse logic functions

Anglický název

On the cascade realization of sparse logic functions

Jazyk

en

Originální abstrakt

Representation of multiple-output logic functions by Multi-Terminal Binary Decision Diagrams (MTBDDs) is studied for the useful class of sparse logic functions specified by the number of true min-terms. This paper derives upper bounds on the MTBDD width, which determine the size of look-up tables (LUTs) needed for hardware realization of these functions in FPGA logic synthesis. The obtained bounds are generalization of similar known bounds for single-output logic functions. Finally a procedure how to find the optimum mapping of MTBDD to a LUT cascade is presented and illustrated on a set of benchmarks.

Anglický abstrakt

Representation of multiple-output logic functions by Multi-Terminal Binary Decision Diagrams (MTBDDs) is studied for the useful class of sparse logic functions specified by the number of true min-terms. This paper derives upper bounds on the MTBDD width, which determine the size of look-up tables (LUTs) needed for hardware realization of these functions in FPGA logic synthesis. The obtained bounds are generalization of similar known bounds for single-output logic functions. Finally a procedure how to find the optimum mapping of MTBDD to a LUT cascade is presented and illustrated on a set of benchmarks.

BibTex


@inproceedings{BUT76311,
  author="Václav {Dvořák} and Petr {Mikušek}",
  title="On the cascade realization of sparse logic functions",
  annote="Representation of multiple-output logic functions by Multi-Terminal Binary
Decision Diagrams (MTBDDs) is studied for the useful class of sparse logic
functions specified by the number of true min-terms. This paper derives upper
bounds on the MTBDD width, which determine the size of look-up tables (LUTs)
needed for hardware realization of these functions in FPGA logic synthesis. The
obtained bounds are generalization of similar known bounds for single-output
logic functions. Finally a procedure how to find the optimum mapping of MTBDD to
a LUT cascade is presented and illustrated on a set of benchmarks.",
  address="IEEE Computer Society",
  booktitle="Euromicro Proceedings",
  chapter="76311",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2011",
  month="april",
  pages="21--28",
  publisher="IEEE Computer Society",
  type="conference paper"
}