Detail publikace

A Global Postsynthesis Optimization Method for Combinational Circuits

VAŠÍČEK, Z. SEKANINA, L.

Originální název

A Global Postsynthesis Optimization Method for Combinational Circuits

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

A genetic programming-based circuit synthesis method is proposed that enables to globally optimize the number of gates in circuits that have already been synthesized using common methods such as ABC and SIS. The main contribution is a proposal for a new fitness function that enables to significantly reduce the fitness evaluation time in comparison to the state of the art. The fitness function performs optimized equivalence checking using a SAT solver. It is shown that the equivalence checking time can significantly be reduced when knowledge of the parent circuit and its mutated offspring is taken into account. For a cost of a runtime, results of conventional synthesis conducted using SIS and ABC were improved by 20-40% for the LGSynth93 benchmarks.

Klíčová slova

logic synthesis, genetic programming, SAT solver

Autoři

VAŠÍČEK, Z.; SEKANINA, L.

Rok RIV

2011

Vydáno

21. 3. 2011

Nakladatel

European Design and Automation Association

Místo

Grenoble

ISBN

978-3-9810801-7-9

Kniha

Proc. of the Design, Automation and Test in Europe DATE 2011

Strany od

1525

Strany do

1528

Strany počet

4

URL

https://www.fit.vut.cz/research/publication/9521/

BibTex

@inproceedings{BUT76297,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="A Global Postsynthesis Optimization Method for Combinational Circuits",
  booktitle="Proc. of the Design, Automation and Test in Europe DATE 2011",
  year="2011",
  pages="1525--1528",
  publisher="European Design and Automation Association",
  address="Grenoble",
  isbn="978-3-9810801-7-9",
  url="https://www.fit.vut.cz/research/publication/9521/"
}