Detail publikace

A Global Postsynthesis Optimization Method for Combinational Circuits

Originální název

A Global Postsynthesis Optimization Method for Combinational Circuits

Anglický název

A Global Postsynthesis Optimization Method for Combinational Circuits

Jazyk

en

Originální abstrakt

A genetic programming-based circuit synthesis method is proposed that enables to globally optimize the number of gates in circuits that have already been synthesized using common methods such as ABC and SIS. The main contribution is a proposal for a new fitness function that enables to significantly reduce the fitness evaluation time in comparison to the state of the art. The fitness function performs optimized equivalence checking using a SAT solver. It is shown that the equivalence checking time can significantly be reduced when knowledge of the parent circuit and its mutated offspring is taken into account. For a cost of a runtime, results of conventional synthesis conducted using SIS and ABC were improved by 20-40% for the LGSynth93 benchmarks.

Anglický abstrakt

A genetic programming-based circuit synthesis method is proposed that enables to globally optimize the number of gates in circuits that have already been synthesized using common methods such as ABC and SIS. The main contribution is a proposal for a new fitness function that enables to significantly reduce the fitness evaluation time in comparison to the state of the art. The fitness function performs optimized equivalence checking using a SAT solver. It is shown that the equivalence checking time can significantly be reduced when knowledge of the parent circuit and its mutated offspring is taken into account. For a cost of a runtime, results of conventional synthesis conducted using SIS and ABC were improved by 20-40% for the LGSynth93 benchmarks.

BibTex


@inproceedings{BUT76297,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="A Global Postsynthesis Optimization Method for Combinational Circuits",
  annote="A genetic programming-based circuit synthesis method is proposed that enables to
globally optimize the number of gates in circuits that have already been
synthesized using common methods such as ABC and SIS. The main contribution is
a proposal for a new fitness function that enables to significantly reduce the
fitness evaluation time in comparison to the state of the art. The fitness
function performs optimized equivalence checking using a SAT solver. It is shown
that the equivalence checking time can significantly be reduced when knowledge of
the parent circuit and its mutated offspring is taken into account. For a cost of
a runtime, results of conventional synthesis conducted using SIS and ABC were
improved by 20-40% for the LGSynth93 benchmarks.",
  address="European Design and Automation Association",
  booktitle="Proc. of the Design, Automation and Test in Europe DATE 2011",
  chapter="76297",
  edition="NEUVEDEN",
  howpublished="print",
  institution="European Design and Automation Association",
  year="2011",
  month="march",
  pages="1525--1528",
  publisher="European Design and Automation Association",
  type="conference paper"
}