Detail publikace

A Programmable Interconnection Network for Multiple Communication Patterns

Originální název

A Programmable Interconnection Network for Multiple Communication Patterns

Anglický název

A Programmable Interconnection Network for Multiple Communication Patterns

Jazyk

en

Originální abstrakt

Application-specific or embedded systems with less than 16 processing cores are too small to use some kind of network on chip (NoC) for interconnection. On the other hand, a crossbar and related circuitry (arbiters, memory elements) are too expensive in terms of chip area. As only few pair-wise and collective communication patterns are mostly used in specific applications, we explore an interconnection network that can support only selected communication patterns and no others. The main contribution of the paper is designing of such networks without routers or arbiters, in a form of programmable combinational logic, with limited crossbar functionality. The interconnection network can be implemented by multiplexers or block RAMs on the FPGA chip at a very low cost. A functional decomposition of the related multiple-output Boolean function into a cascade of block RAM devices is aided by multi-terminal binary decision diagrams and is illustrated on examples.

Anglický abstrakt

Application-specific or embedded systems with less than 16 processing cores are too small to use some kind of network on chip (NoC) for interconnection. On the other hand, a crossbar and related circuitry (arbiters, memory elements) are too expensive in terms of chip area. As only few pair-wise and collective communication patterns are mostly used in specific applications, we explore an interconnection network that can support only selected communication patterns and no others. The main contribution of the paper is designing of such networks without routers or arbiters, in a form of programmable combinational logic, with limited crossbar functionality. The interconnection network can be implemented by multiplexers or block RAMs on the FPGA chip at a very low cost. A functional decomposition of the related multiple-output Boolean function into a cascade of block RAM devices is aided by multi-terminal binary decision diagrams and is illustrated on examples.

BibTex


@inproceedings{BUT76259,
  author="Václav {Dvořák} and Jiří {Jaroš}",
  title="A Programmable Interconnection Network for Multiple Communication Patterns",
  annote="Application-specific or embedded systems with less than 16 processing cores are
too small to use some kind of network on chip (NoC) for interconnection. On the
other hand, a crossbar and related circuitry (arbiters, memory elements) are too
expensive in terms of chip area. As only few pair-wise and collective
communication patterns are mostly used in specific applications, we explore an
interconnection network that can support only selected communication patterns and
no others. The main contribution of the paper is designing of such networks
without routers or arbiters, in a form of programmable combinational logic, with
limited crossbar functionality. The interconnection network can be implemented by
multiplexers or block RAMs on the FPGA chip at a very low cost. A functional
decomposition of the related multiple-output Boolean function into a cascade of
block RAM devices is aided by multi-terminal binary decision diagrams and is
illustrated on examples.",
  address="International Academy, Research, and Industry Association",
  booktitle="Proceedings of the Sixth International Conference on Systems, ICONS 2011",
  chapter="76259",
  edition="NEUVEDEN",
  howpublished="print",
  institution="International Academy, Research, and Industry Association",
  year="2011",
  month="january",
  pages="6--11",
  publisher="International Academy, Research, and Industry Association",
  type="conference paper"
}