Detail publikace

FPGA-based In-system Jitter Measurement

Originální název

FPGA-based In-system Jitter Measurement

Anglický název

FPGA-based In-system Jitter Measurement

Jazyk

en

Originální abstrakt

The paper presents a simple jitter measurement device implemented in FPGA. The device for the jitter measurement is closely coupled with a blind oversampling data recovery circuit (BO-CDR), which is sometimes used in asynchronous high speed data receivers as an alternative to the traditional PLL-based CDR circuit. The jitter measurement itself is based on estimating the edge density distribution over one unit interval via evaluating the number of detected edges in particular time intervals. The method enables simultaneous data transmission and real-time signal quality estimation without affecting the data signal, which is probably the main benefit of the proposed solution. There is no need for any additional hardware except the FPGA. The jitter evaluation is done completely within the gate array, requiring a few of its hardware resources. The proposed device was successfully implemented and tested on an optical data link. Real measurement results are presented together with reference measurements acquired using an oscilloscope.

Anglický abstrakt

The paper presents a simple jitter measurement device implemented in FPGA. The device for the jitter measurement is closely coupled with a blind oversampling data recovery circuit (BO-CDR), which is sometimes used in asynchronous high speed data receivers as an alternative to the traditional PLL-based CDR circuit. The jitter measurement itself is based on estimating the edge density distribution over one unit interval via evaluating the number of detected edges in particular time intervals. The method enables simultaneous data transmission and real-time signal quality estimation without affecting the data signal, which is probably the main benefit of the proposed solution. There is no need for any additional hardware except the FPGA. The jitter evaluation is done completely within the gate array, requiring a few of its hardware resources. The proposed device was successfully implemented and tested on an optical data link. Real measurement results are presented together with reference measurements acquired using an oscilloscope.

Dokumenty

BibTex


@inproceedings{BUT74718,
  author="Michal {Kubíček} and Zdeněk {Kolka}",
  title="FPGA-based In-system Jitter Measurement",
  annote="The paper presents a simple jitter measurement device implemented in FPGA. The device for the jitter measurement is closely coupled with a blind oversampling data recovery circuit (BO-CDR), which is sometimes used in asynchronous high speed data receivers as an alternative to the traditional PLL-based CDR circuit. The jitter measurement itself is based on estimating the edge density distribution over one unit interval via evaluating the number of detected edges in particular time intervals.
The method enables simultaneous data transmission and real-time signal quality estimation without affecting the data signal, which is probably the main benefit of the proposed solution. There is no need for any additional hardware except the FPGA. The jitter evaluation is done completely within the gate array, requiring a few of its hardware resources.
The proposed device was successfully implemented and tested on an optical data link. Real measurement results are presented together with reference measurements acquired using an oscilloscope.",
  address="Fakulta elektrotechniky, ČVUT",
  booktitle="ISMOT Proceedings 2011",
  chapter="74718",
  edition="1",
  howpublished="electronic, physical medium",
  institution="Fakulta elektrotechniky, ČVUT",
  year="2011",
  month="november",
  pages="277--280",
  publisher="Fakulta elektrotechniky, ČVUT",
  type="conference paper"
}