Detail publikace

VHDL Procedure for Combinational Divider

FEDRA, Z. KOLOUCH, J.

Originální název

VHDL Procedure for Combinational Divider

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices - amount of FPGA resources used and maximum delay, are given in tables.

Klíčová slova

divider, FPGA, implementation, procedure, static timing analysis, VHDL

Autoři

FEDRA, Z.; KOLOUCH, J.

Rok RIV

2011

Vydáno

20. 8. 2011

ISBN

978-1-4577-1761-1

Kniha

34th International Conference on Telecommunications and Signal Processing, TSP 2011

Strany od

469

Strany do

471

Strany počet

3

BibTex

@inproceedings{BUT74709,
  author="Zbyněk {Fedra} and Jaromír {Kolouch}",
  title="VHDL Procedure for Combinational Divider",
  booktitle="34th International Conference on Telecommunications and Signal Processing, TSP 2011",
  year="2011",
  pages="469--471",
  isbn="978-1-4577-1761-1"
}