Detail publikace

Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study

Originální název

Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study

Anglický název

Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study

Jazyk

en

Originální abstrakt

The paper addresses the issue of prototyping hw/sw architecture of application-specific multi-processor systems (recently on a chip). Performance prediction of these systems, either bus-based SMPs or message-passing networks of DSPs, is undertaken using a CSP-based tool Transim. Variations in processor count, clock rate, link speed, bus bandwidth, cache line, as well as in partitioning and mapping the resulting sw components to processors can be easily accounted for. The technique is demonstrated on parallel FFT on 2 to 8 processors.

Anglický abstrakt

The paper addresses the issue of prototyping hw/sw architecture of application-specific multi-processor systems (recently on a chip). Performance prediction of these systems, either bus-based SMPs or message-passing networks of DSPs, is undertaken using a CSP-based tool Transim. Variations in processor count, clock rate, link speed, bus bandwidth, cache line, as well as in partitioning and mapping the resulting sw components to processors can be easily accounted for. The technique is demonstrated on parallel FFT on 2 to 8 processors.

BibTex 


@inproceedings{BUT5579,
  author="Václav {Dvořák}",
  title="Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study",
  annote="The paper addresses the issue of prototyping hw/sw architecture of application-specific multi-processor systems (recently on a chip). Performance prediction of these systems, either  bus-based SMPs or message-passing networks of DSPs, is undertaken using a CSP-based tool Transim. Variations in processor count, clock rate, link speed, bus bandwidth, cache line,  as well as in partitioning and mapping the resulting sw components to processors can be easily accounted for. The technique is demonstrated on parallel FFT on 2 to 8 processors.",
  address="Publishing House of Zielona Gora Technical University",
  booktitle="Proceedings of the the International Workshop on Discrete-Event System Design, DESDes'01",
  chapter="5579",
  institution="Publishing House of Zielona Gora Technical University",
  year="2001",
  month="january",
  pages="103--108",
  publisher="Publishing House of Zielona Gora Technical University",
  type="conference paper"
}