Detail publikace

Optimizing Communication Architectures for Parallel Embedded Systems

Originální název

Optimizing Communication Architectures for Parallel Embedded Systems

Anglický název

Optimizing Communication Architectures for Parallel Embedded Systems

Jazyk

en

Originální abstrakt

The paper addresses  the issue of prototyping group communications in application-specific multi-processor systems or SoC. Group communications may have a dramatic impact on the performance and this is why performance estimation of these systems, either bus-based SMPs or message-passing networks of DSPs is undertaken using a CSP-based tool Transim. Variations in computation granularity, communication algorithms, interconnect topology, distribution of data and code to processors as well as in processor count, clock rate, link speed, bus bandwidth, cache line size and other parameters can be easily accounted for. The technique is demonstrated on parallel FFT on 2 to 8 processors.

Anglický abstrakt

The paper addresses  the issue of prototyping group communications in application-specific multi-processor systems or SoC. Group communications may have a dramatic impact on the performance and this is why performance estimation of these systems, either bus-based SMPs or message-passing networks of DSPs is undertaken using a CSP-based tool Transim. Variations in computation granularity, communication algorithms, interconnect topology, distribution of data and code to processors as well as in processor count, clock rate, link speed, bus bandwidth, cache line size and other parameters can be easily accounted for. The technique is demonstrated on parallel FFT on 2 to 8 processors.

BibTex


@inbook{BUT55530,
  author="Václav {Dvořák}",
  title="Optimizing Communication Architectures for Parallel Embedded Systems",
  annote="The paper addresses  the issue of prototyping group communications in application-specific multi-processor systems or SoC. Group communications may have a dramatic impact on the performance and this is why performance estimation of these systems, either bus-based SMPs or message-passing networks of DSPs is undertaken using a CSP-based tool Transim. Variations in computation granularity, communication algorithms, interconnect topology, distribution of data and code to processors as well as in processor count, clock rate, link speed, bus bandwidth, cache line size and other parameters can be easily accounted for. The technique is demonstrated on parallel FFT on 2 to 8 processors.",
  address="Springer Verlag",
  booktitle="Design of Embedded Control Systems",
  chapter="55530",
  institution="Springer Verlag",
  year="2004",
  month="may",
  pages="225--234",
  publisher="Springer Verlag",
  type="book chapter"
}