Detail publikace

Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units

VAŠÍČEK, Z. SEKANINA, L.

Originální název

Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units

Typ

článek v časopise - ostatní, Jost

Jazyk

angličtina

Originální abstrakt

A new accelerator of Cartesian genetic programming is presented in this paper. The accelerator is completely implemented in a single FPGA. The proposed architecture contains multiple instances of virtual reconfigurable circuit to evaluate several candidate solutions in parallel. An advanced memory organization was developed to achieve the maximum throughput of processing. The search algorithm is implemented using the on-chip PowerPC processor. In the benchmark problem (image filter evolution) the proposed platform provides a significant speedup (170) in comparison with a highly optimized software implementation. Moreover, the accelerator is 8 times faster than previous FPGA accelerators of image filter evolution.

Klíčová slova

Cartesian genetic programming, hardware accelerator, evolutionary circuit design, FPGA

Autoři

VAŠÍČEK, Z.; SEKANINA, L.

Rok RIV

2010

Vydáno

31. 12. 2010

ISSN

1335-9150

Periodikum

Computing and Informatics

Ročník

29

Číslo

6

Stát

Slovenská republika

Strany od

1359

Strany do

1371

Strany počet

13

URL

https://www.fit.vut.cz/research/publication/9421/

BibTex

@article{BUT50732,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units",
  journal="Computing and Informatics",
  year="2010",
  volume="29",
  number="6",
  pages="1359--1371",
  issn="1335-9150",
  url="https://www.fit.vut.cz/research/publication/9421/"
}