Detail publikace

Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties

Originální název

Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties

Anglický název

Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties

Jazyk

en

Originální abstrakt

The paper presents testability analysis method that is based on partitioning circuit under analysis (CUA) into testable blocks (TBs). The concept of TBs is further utilized for power consumption reduction during the test application. Software tools which were developed during the research and integrated into the third party design flow are also described. The experimental results gained from the application of the methodology on selected benchmarks and practical designs are demonstrated. It was proven on the benchmarks, used for the verification of the methodology, that a fault coverage comparable to the partial scan method can be obtained. When combined with test vectors/scan cells reordering methodology significant power savings can be reached.

Anglický abstrakt

The paper presents testability analysis method that is based on partitioning circuit under analysis (CUA) into testable blocks (TBs). The concept of TBs is further utilized for power consumption reduction during the test application. Software tools which were developed during the research and integrated into the third party design flow are also described. The experimental results gained from the application of the methodology on selected benchmarks and practical designs are demonstrated. It was proven on the benchmarks, used for the verification of the methodology, that a fault coverage comparable to the partial scan method can be obtained. When combined with test vectors/scan cells reordering methodology significant power savings can be reached.

BibTex


@article{BUT49469,
  author="Jaroslav {Škarvada} and Zdeněk {Kotásek} and Tomáš {Herrman}",
  title="Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties",
  annote="The paper presents testability analysis method that is based on partitioning
circuit under analysis (CUA) into testable blocks (TBs). The concept of TBs is
further utilized for power consumption reduction during the test application.
Software tools which were developed during the research and integrated into the
third party design flow are also described. The experimental results gained from
the application of the methodology on selected benchmarks and practical designs
are demonstrated. It was proven on the benchmarks, used for the verification of
the methodology, that a fault coverage comparable to the partial scan method can
be obtained. When combined with test vectors/scan cells reordering methodology
significant power savings can be reached.",
  address="NEUVEDEN",
  booktitle="Microprocessors and Microsystems, Dependability and Testing of Modern Digital Systems",
  chapter="49469",
  edition="NEUVEDEN",
  howpublished="print",
  institution="NEUVEDEN",
  journal="Microprocessors and Microsystems",
  number="5",
  volume="32",
  year="2008",
  month="april",
  pages="296--302",
  publisher="NEUVEDEN",
  type="journal article - other"
}