Detail publikace

Methodology for Design of Highly Dependable Systems in FPGA

Originální název

Methodology for Design of Highly Dependable Systems in FPGA

Anglický název

Methodology for Design of Highly Dependable Systems in FPGA

Jazyk

en

Originální abstrakt

In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design highly dependable system in FPGA is described. First, our experiences with partial dynamic reconfiguration in FPGA and application of partial reconfiguration as advanced solution for constructing of different types of fault tolerant architectures are described. Secondly, the main principles of methodology and first experiments with real fault tolerant designs based on partial dynamic reconfiguration implemented into Virtex5 and latest Virtex6 FPGAs are demonstrated.

Anglický abstrakt

In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design highly dependable system in FPGA is described. First, our experiences with partial dynamic reconfiguration in FPGA and application of partial reconfiguration as advanced solution for constructing of different types of fault tolerant architectures are described. Secondly, the main principles of methodology and first experiments with real fault tolerant designs based on partial dynamic reconfiguration implemented into Virtex5 and latest Virtex6 FPGAs are demonstrated.

BibTex


@inproceedings{BUT35527,
  author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}",
  title="Methodology for Design of Highly Dependable Systems in FPGA",
  annote="In the paper, a survey of our research activities the goal of which is to develop
a methodology allowing to design highly dependable system in FPGA is described.
First, our experiences with partial dynamic reconfiguration in FPGA and
application of partial reconfiguration as advanced solution for constructing of
different types of fault tolerant architectures are described. Secondly, the main
principles of methodology and first experiments with real fault tolerant designs
based on partial dynamic reconfiguration implemented into Virtex5 and latest
Virtex6 FPGAs are demonstrated.",
  address="The University of Technology Košice",
  booktitle="International Scientific Conference on Computer Science and Engineering",
  chapter="35527",
  edition="NEUVEDEN",
  howpublished="print",
  institution="The University of Technology Košice",
  year="2010",
  month="june",
  pages="186--193",
  publisher="The University of Technology Košice",
  type="conference paper"
}