Detail publikace

Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing

KAŠTIL, J. KOŘENEK, J.

Originální název

Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

With the increased amount of data transferred by computer networks, the amount of the malicious traffic also increases and therefore it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. Pattern matching is the time critical operation of current IDS. This paper deals with the analysis of regular expressions used by modern IDS to describe malicious traffic. According to our analysis, more than 64 percent of regular expressions create Deterministic Finite Automaton (DFA) with less than 20 percent of saturation of the transition table which allows efficient implementation of pattern matching into FPGA platform. We propose architecture for fast pattern matching using perfect hashing suitable for implementation into FPGA platform. The memory requirements of presented architecture is closed to the theoretical minimum for sparse transition tables.

Klíčová slova

Intrusion Detection, Perfect Hashing,hardware acceleration, Deterministic Finite Automata

Autoři

KAŠTIL, J.; KOŘENEK, J.

Rok RIV

2010

Vydáno

19. 4. 2010

Nakladatel

IEEE Computer Society

Místo

Vienna

ISBN

978-1-4244-6610-8

Kniha

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010

Strany od

149

Strany do

152

Strany počet

4

URL

https://www.fit.vut.cz/research/publication/9200/

BibTex

@inproceedings{BUT35426,
  author="Jan {Kaštil} and Jan {Kořenek}",
  title="Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing",
  booktitle="Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010",
  year="2010",
  pages="149--152",
  publisher="IEEE Computer Society",
  address="Vienna",
  isbn="978-1-4244-6610-8",
  url="https://www.fit.vut.cz/research/publication/9200/"
}