Detail publikace

Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time

Originální název

Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time

Anglický název

Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time

Jazyk

en

Originální abstrakt

Recently, a method has been presented that allows a significant test application time reduction if some of gates of a digital circuit are reconfigured before test is applied. Selection of the gates for reconfiguration was performed using a very time consuming deterministic recursive search algorithm. In this paper, a new method is proposed for selection of the gates in order to reduce the test application time. The method utilizes an evolutionary algorithm which is able to discover very competitive reconfiguration strategies while the time of optimization is considerably reduced with respect to the original algorithm. Moreover, the user can easily balance the trade off between the number of test vectors and amount of logic that has to be reconfigured. Experimental results are reported for the ISCAS85 benchmark suite.

Anglický abstrakt

Recently, a method has been presented that allows a significant test application time reduction if some of gates of a digital circuit are reconfigured before test is applied. Selection of the gates for reconfiguration was performed using a very time consuming deterministic recursive search algorithm. In this paper, a new method is proposed for selection of the gates in order to reduce the test application time. The method utilizes an evolutionary algorithm which is able to discover very competitive reconfiguration strategies while the time of optimization is considerably reduced with respect to the original algorithm. Moreover, the user can easily balance the trade off between the number of test vectors and amount of logic that has to be reconfigured. Experimental results are reported for the ISCAS85 benchmark suite.

BibTex


@inproceedings{BUT34847,
  author="Jiří {Šimáček} and Lukáš {Sekanina} and Lukáš {Stareček}",
  title="Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time",
  annote="Recently, a method has been presented that allows a significant test application
time reduction if some of gates of a digital circuit are reconfigured before test
is applied. Selection of the gates for reconfiguration was performed using a very
time consuming deterministic recursive search algorithm. In this paper, a new
method is proposed for selection of the gates in order to reduce the test
application time. The method utilizes an evolutionary algorithm which is able to
discover very competitive reconfiguration strategies while the time of
optimization is considerably reduced with respect to the original algorithm.
Moreover, the user can easily balance the trade off between the number of test
vectors and amount of logic that has to be reconfigured. Experimental results are
reported for the ISCAS85 benchmark suite.",
  address="Springer Verlag",
  booktitle="Evolvable Systems: From Biology to Hardware",
  chapter="34847",
  edition="Lecture Notes in Computer Science",
  howpublished="print",
  institution="Springer Verlag",
  year="2010",
  month="september",
  pages="214--225",
  publisher="Springer Verlag",
  type="conference paper"
}