Detail publikace

IMPROVED DESIGN FOR MODULO 2n+1 ADDER

YOUNES, D. ŠTEFFAN, P.

Originální název

IMPROVED DESIGN FOR MODULO 2n+1 ADDER

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

2n + 1 modular adders are widely used in Residue Number System arithmetic. Their performance is restricted due to the hardware implementation complexity. In this paper a novel circuit design for 2n + 1 adder has been proposed. This design reduces the bit length of operands used in most 2n + 1 residue adders from (n+1) to n bit long. Thereby complexity of VLSI implementation and delay of the overall system will be reduced. The proposed circuit has been implemented using VHDL to prove the theoretical consideration.

Klíčová slova

Residue Number System, 2n + 1 adder, modular adder, subtractor

Autoři

YOUNES, D.; ŠTEFFAN, P.

Rok RIV

2010

Vydáno

1. 9. 2010

Místo

Brno

ISBN

978-80-214-4138-5

Kniha

Electronic Devices and Systems IMAPS CS International Conference 2010

Strany od

346

Strany do

348

Strany počet

3

BibTex

@inproceedings{BUT34792,
  author="Dina {Younes} and Pavel {Šteffan}",
  title="IMPROVED DESIGN FOR MODULO 2n+1 ADDER",
  booktitle="Electronic Devices and Systems IMAPS CS International Conference 2010",
  year="2010",
  pages="346--348",
  address="Brno",
  isbn="978-80-214-4138-5"
}