Detail publikace

Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration

Originální název

Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration

Anglický název

Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration

Jazyk

en

Originální abstrakt

In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.

Anglický abstrakt

In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.

BibTex


@inproceedings{BUT34654,
  author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}",
  title="Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration",
  annote="In this paper, activities which aim at developing a methodology of fault tolerant
systems design into SRAM-based FPGA platforms with different types of diagnostic
approaches are presented. Basic principles of partial dynamic reconfiguration are
described together with their impact on the fault tolerance of the digital design
in FPGA. A generic controller for driving dynamic reconfiguration process of
faulty unit is demonstrated and analyzed. Parameters of the generic partial
reconfiguration controller are experimentally verified. The developed controller
is compared with other approaches based on micro-controllers inside FPGA.
A structure which can be used in fault tolerant system design into SRAM-based
FPGA using partial reconfiguration controller is then described. The presented
structure is proven fully functional on the ML506 development board for different
types of RTL components.",
  address="IEEE Computer Society",
  booktitle="13th EUROMICRO Conference on Digital System Design, DSD'2010",
  chapter="34654",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2010",
  month="april",
  pages="365--372",
  publisher="IEEE Computer Society",
  type="conference paper"
}