Detail publikace

Memory Optimization for Packet Classification Algorithms in FPGA

KOŘENEK, J. PUŠ, V.

Originální název

Memory Optimization for Packet Classification Algorithms in FPGA

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

Packet classification algorithms are widely used in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays hardware architectures can achieve multigigabit speeds only at the cost of large data structures, which can not fit into the on-chip memory. We propose novel method how to reduce data structure size for the family of decomposition architectures at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the Cartesian product nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed.

Klíčová slova

packet classification, sram, fpga, tcam

Autoři

KOŘENEK, J.; PUŠ, V.

Rok RIV

2010

Vydáno

14. 4. 2010

Nakladatel

IEEE Computer Society

Místo

Vídeň

ISBN

978-1-4244-6610-8

Kniha

Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

Strany od

297

Strany do

300

Strany počet

4

URL

https://www.fit.vut.cz/research/publication/9198/

BibTex

@inproceedings{BUT34651,
  author="Jan {Kořenek} and Viktor {Puš}",
  title="Memory Optimization for Packet Classification Algorithms in FPGA",
  booktitle="Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  year="2010",
  pages="297--300",
  publisher="IEEE Computer Society",
  address="Vídeň",
  isbn="978-1-4244-6610-8",
  url="https://www.fit.vut.cz/research/publication/9198/"
}