Detail publikace

Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs

STRAKA, M. KAŠTIL, J. KOTÁSEK, Z.

Originální název

Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs

Anglický název

Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs

Jazyk

en

Originální abstrakt

Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.

Anglický abstrakt

Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.

Dokumenty

BibTex


@inproceedings{BUT34646,
  author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}",
  title="Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs",
  annote="Activities which aim at developing a methodology of fault tolerant systems design
into FPGA platforms are presented. Basic principles of partial reconfiguration
are described together with the fault tolerant architectures based on the partial
dynamic reconfiguration and triple modular redundancy or duplex system. Several
architectures using online checkers for error detection which initiates
reconfiguration process of the faulty unit are introduced as well. The
modification of fault tolerant architectures into partial reconfigurable modules
and main advantages of partial dynamic reconfiguration when used in fault
tolerant system design are demonstrated. All presented architectures are compared
with each other and proven fully functional on the ML506 development board with
Virtex5 for different types of RTL digital components.",
  address="IEEE Computer Society",
  booktitle="Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010",
  chapter="34646",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2010",
  month="february",
  pages="173--176",
  publisher="IEEE Computer Society",
  type="conference paper"
}