Detail publikace

Reliability Models for Fault Tolerant Architectures Based on FPGA

Originální název

Reliability Models for Fault Tolerant Architectures Based on FPGA

Anglický název

Reliability Models for Fault Tolerant Architectures Based on FPGA

Jazyk

en

Originální abstrakt

In this presentation, a methodology of FTS design based on FPGA is presented. The FT architectures are based both on duplex and TMR systems to which fault detection capabilities are added, the use of on-line checkers for this purpose is demonstrated. It is described how reliability and availability parameters in TMR and duplex structures with checkers can be increased. To demonstrate this, analytical calculations based on Markov reliability model are used. It is also shown how the availability parameters can be affected by the operating environment into which the FTS is implemented. Finally, the results of research and the comparison of our approach with classical TMR and duplex architectures for different failure rates are presented.

Anglický abstrakt

In this presentation, a methodology of FTS design based on FPGA is presented. The FT architectures are based both on duplex and TMR systems to which fault detection capabilities are added, the use of on-line checkers for this purpose is demonstrated. It is described how reliability and availability parameters in TMR and duplex structures with checkers can be increased. To demonstrate this, analytical calculations based on Markov reliability model are used. It is also shown how the availability parameters can be affected by the operating environment into which the FTS is implemented. Finally, the results of research and the comparison of our approach with classical TMR and duplex architectures for different failure rates are presented.

BibTex


@inproceedings{BUT33747,
  author="Martin {Straka} and Zdeněk {Kotásek}",
  title="Reliability Models for Fault Tolerant Architectures Based on FPGA",
  annote="In this presentation, a methodology of FTS design based on FPGA is
presented. The FT architectures are based both on duplex and TMR
systems to which fault detection capabilities are added, the use
of on-line checkers for this purpose is demonstrated. It is
described how reliability and availability parameters in TMR and
duplex structures with checkers can be increased. To demonstrate
this, analytical calculations based on Markov reliability model
are used. It is also shown how the availability parameters can be
affected by the operating environment into which the FTS is
implemented. Finally, the results of research and the comparison
of our approach with classical TMR and duplex architectures for
different failure rates are presented.",
  address="Faculty of Informatics MU",
  booktitle="5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  chapter="33747",
  edition="NEUVEDEN",
  howpublished="print",
  institution="Faculty of Informatics MU",
  year="2009",
  month="october",
  pages="239--239",
  publisher="Faculty of Informatics MU",
  type="conference paper"
}