Detail publikace

Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming

Originální název

Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming

Anglický název

Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming

Jazyk

en

Originální abstrakt

Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the gate level. However, this approach is not scalable. Experimental results presented in this paper indicate that larger and more efficient polymorphic circuits can be designed by a combination of conventional design methods and evolutionary optimization (conducted by CGP). Proposed methods are evaluated on two benchmark circuits of variable input size.

Anglický abstrakt

Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the gate level. However, this approach is not scalable. Experimental results presented in this paper indicate that larger and more efficient polymorphic circuits can be designed by a combination of conventional design methods and evolutionary optimization (conducted by CGP). Proposed methods are evaluated on two benchmark circuits of variable input size.

BibTex


@inproceedings{BUT33725,
  author="Zbyšek {Gajda} and Lukáš {Sekanina}",
  title="Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming",
  annote="Polymorphic digital circuits contain ordinary and polymorphic gates. In the past,
Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic
circuits at the gate level. However, this approach is not scalable. Experimental
results presented in this paper indicate that larger and more efficient
polymorphic circuits can be designed by a combination of conventional design
methods and evolutionary optimization (conducted by CGP). Proposed methods are
evaluated on two benchmark circuits of variable input size.",
  address="IEEE Computational Intelligence Society",
  booktitle="Proc. of 2009 IEEE Congress on Evolutionary Computation",
  chapter="33725",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computational Intelligence Society",
  year="2009",
  month="may",
  pages="1599--1604",
  publisher="IEEE Computational Intelligence Society",
  type="conference paper"
}