Detail publikace

The Design of Hardware Checkers for Verification and Diagnostic Purposes

Originální název

The Design of Hardware Checkers for Verification and Diagnostic Purposes

Anglický název

The Design of Hardware Checkers for Verification and Diagnostic Purposes

Jazyk

en

Originální abstrakt

In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers of digital components is described. First, our experiments with PSL language and FoCs tool are demonstrated. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principles of our approach based on developing a formal language to describe the functions to be checked and a compiler which transforms the description into VHDL code are explained.

Anglický abstrakt

In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers of digital components is described. First, our experiments with PSL language and FoCs tool are demonstrated. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principles of our approach based on developing a formal language to describe the functions to be checked and a compiler which transforms the description into VHDL code are explained.

BibTex


@inproceedings{BUT32103,
  author="Martin {Straka} and Zdeněk {Kotásek} and Jan {Winter}",
  title="The Design of Hardware Checkers for Verification and Diagnostic Purposes",
  annote="In the paper, a survey of our research activities the goal of which is to develop
a methodology allowing to design on-line checkers of digital components is
described. First, our experiments with PSL language and FoCs tool are
demonstrated. It is shown how PSL can be used to describe conditions to be
checked by an on-line checker of a digital component. It is demonstrated that
checkers generated from PSL description demand more sources than the unit under
check which is seen as unacceptable result. The principles of our approach based
on developing a formal language to describe the functions to be checked and
a compiler which transforms the description into VHDL code are explained.",
  address="The University of Technology Košice",
  booktitle="CSE'2008 International Scientific Conference on Computer Science and Engineering",
  chapter="32103",
  edition="NEUVEDEN",
  howpublished="print",
  institution="The University of Technology Košice",
  year="2008",
  month="june",
  pages="320--327",
  publisher="The University of Technology Košice",
  type="conference paper"
}