Detail publikace

Hardware Accelerators for Cartesian Genetic Programming

VAŠÍČEK, Z. SEKANINA, L.

Originální název

Hardware Accelerators for Cartesian Genetic Programming

Anglický název

Hardware Accelerators for Cartesian Genetic Programming

Jazyk

en

Originální abstrakt

A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP).  The accelerators contain a genetic engine which is reused in all applications. Candidate programs (circuits) are evaluated using application-specific virtual reconfigurable circuit (VRC) and fitness unit. Two types of VRCs are proposed. The first one is devoted for symbolic regression problems over the fixed point representation. The second one is designed for evolution of logic circuits. In both cases a significant speedup of evolution (30-40 times) was obtained in comparison with a highly optimized software implementation of CGP. This speedup can be increased by creating multiple fitness units.

Anglický abstrakt

A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP).  The accelerators contain a genetic engine which is reused in all applications. Candidate programs (circuits) are evaluated using application-specific virtual reconfigurable circuit (VRC) and fitness unit. Two types of VRCs are proposed. The first one is devoted for symbolic regression problems over the fixed point representation. The second one is designed for evolution of logic circuits. In both cases a significant speedup of evolution (30-40 times) was obtained in comparison with a highly optimized software implementation of CGP. This speedup can be increased by creating multiple fitness units.

Dokumenty

BibTex


@inproceedings{BUT30754,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Hardware Accelerators for Cartesian Genetic Programming",
  annote="A new class of FPGA-based accelerators is presented for Cartesian Genetic
Programming (CGP).  The accelerators contain a genetic engine which is reused in
all applications. 
Candidate programs (circuits) are evaluated using application-specific virtual
reconfigurable circuit (VRC) and fitness unit. Two types of VRCs are proposed.
The first one is devoted for symbolic regression problems over the fixed point
representation. The second one is designed for evolution of logic circuits. In
both cases a significant speedup of evolution (30-40 times) was obtained in
comparison with a highly optimized software implementation of CGP. This speedup
can be increased by creating multiple fitness units.",
  address="Springer Verlag",
  booktitle="Eleventh European Conference on Genetic Programming",
  chapter="30754",
  edition="Lecture Notes in Computer Science",
  howpublished="print",
  institution="Springer Verlag",
  journal="Lecture Notes in Computer Science (IF 0,513)",
  year="2008",
  month="march",
  pages="230--241",
  publisher="Springer Verlag",
  type="conference paper"
}