Detail publikace

Power Conscious RTL Test Scheduling

ŠKARVADA, J. KOTÁSEK, Z. HERRMAN, T.

Originální název

Power Conscious RTL Test Scheduling

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

In the paper, a methodology for power conscious RTL test scheduling is presented. At first the circuit under analysis (CUA) is mapped into technological library and partitioned. For each partition the sequences of test vectors are generated and if possible also reordered in order to reduce power consumption during the test application. For the test scheduling the Integer Linear Programming (ILP) model is used. The goal of the methodology is to find the test schedule with lowest test application time and with power consumption less than the allowed limit.

Klíčová slova

RTL test scheduling, power consumption, circuit partitioning, testable blocks

Autoři

ŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T.

Rok RIV

2008

Vydáno

14. 10. 2008

Nakladatel

Masaryk University

Místo

Znojmo

ISBN

978-80-7355-082-0

Kniha

4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

Strany od

265

Strany do

265

Strany počet

1

URL

https://www.fit.vut.cz/research/publication/8795/

BibTex

@inproceedings{BUT30718,
  author="Jaroslav {Škarvada} and Zdeněk {Kotásek} and Tomáš {Herrman}",
  title="Power Conscious RTL Test Scheduling",
  booktitle="4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2008",
  pages="265--265",
  publisher="Masaryk University",
  address="Znojmo",
  isbn="978-80-7355-082-0",
  url="https://www.fit.vut.cz/research/publication/8795/"
}