Detail publikace

Checkers Design for Communication Protocols Based on FPGAs

Originální název

Checkers Design for Communication Protocols Based on FPGAs

Anglický název

Checkers Design for Communication Protocols Based on FPGAs

Jazyk

en

Originální abstrakt

In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used to check the communication between IP cores implemented in FPGA. The checker watches the communication and detects such states which do not satisfy protocol definitions. If such a situation appears, it is indicated that hardware implementation does not work properly. The communication must be precisely defined - for this purpose, a formal approach was developed which allows to describe ambiguously the conditions which must be satisfied during the communication. From the description, the checker description in VHDL is generated (a compiler was developed for this purpose) and implemented into FPGA. The methodology was verified on LocalLink communication protocol developed by Xilinx, Virtex 2 Pro and Virtex4 FPGAs were used for the implementation.

Anglický abstrakt

In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used to check the communication between IP cores implemented in FPGA. The checker watches the communication and detects such states which do not satisfy protocol definitions. If such a situation appears, it is indicated that hardware implementation does not work properly. The communication must be precisely defined - for this purpose, a formal approach was developed which allows to describe ambiguously the conditions which must be satisfied during the communication. From the description, the checker description in VHDL is generated (a compiler was developed for this purpose) and implemented into FPGA. The methodology was verified on LocalLink communication protocol developed by Xilinx, Virtex 2 Pro and Virtex4 FPGAs were used for the implementation.

BibTex


@inproceedings{BUT30481,
  author="Martin {Straka}",
  title="Checkers Design for Communication Protocols Based on FPGAs",
  annote="In the paper, the principles of a unit design which can be used for on-line
communication protocol checking is presented. It is shown how the checker can be
used to check the communication between IP cores implemented in FPGA. The checker
watches the communication and detects such states which do not satisfy protocol
definitions. If such a situation appears, it is indicated that hardware
implementation does not work properly. The communication must be precisely
defined - for this purpose, a formal approach was developed which allows to
describe ambiguously the conditions which must be satisfied during the
communication. From the description, the checker description in VHDL is generated
(a compiler was developed for this purpose) and implemented into FPGA. The
methodology was verified on LocalLink communication protocol developed by Xilinx,
Virtex 2 Pro and Virtex4 FPGAs were used for the implementation.",
  address="Faculty of Information Technology BUT",
  booktitle="Proceedings of the 14th Conference STUDENT EEICT 2008 Volume 4",
  chapter="30481",
  edition="NEUVEDEN",
  howpublished="print",
  institution="Faculty of Information Technology BUT",
  year="2008",
  month="april",
  pages="467--473",
  publisher="Faculty of Information Technology BUT",
  type="conference paper"
}