Detail publikace

High Availability Fault Tolerant Architectures Implemented into FPGAs

Originální název

High Availability Fault Tolerant Architectures Implemented into FPGAs

Anglický název

High Availability Fault Tolerant Architectures Implemented into FPGAs

Jazyk

en

Originální abstrakt

In the paper, the methodology of fault tolerant systems design based on FPGA are presented. The architectures are based both on duplex and TMR systems to which fault detection capabilities are added, the use of on-line checkers for this purpose is demonstrated. It is described how reliability and availability parameters in TMR and duplex structures with checkers can be increased. To demonstrate this, analytical calculations based on Markov reliability model are used. It is also shown how the availability parameters can be affected by the operating environment into which the fault tolerant system is implemented. The principles of generating sequence of FT architectures with different level of diagnostic are presented.

Anglický abstrakt

In the paper, the methodology of fault tolerant systems design based on FPGA are presented. The architectures are based both on duplex and TMR systems to which fault detection capabilities are added, the use of on-line checkers for this purpose is demonstrated. It is described how reliability and availability parameters in TMR and duplex structures with checkers can be increased. To demonstrate this, analytical calculations based on Markov reliability model are used. It is also shown how the availability parameters can be affected by the operating environment into which the fault tolerant system is implemented. The principles of generating sequence of FT architectures with different level of diagnostic are presented.

BibTex


@inproceedings{BUT30207,
  author="Martin {Straka} and Zdeněk {Kotásek}",
  title="High Availability Fault Tolerant Architectures Implemented into FPGAs",
  annote="In the paper, the methodology of fault tolerant systems design based on FPGA are
presented. The architectures are based both on duplex and TMR systems to which
fault detection capabilities are added, the use of on-line checkers for this
purpose is demonstrated. It is described how reliability and availability
parameters in TMR and duplex structures with checkers can be increased. To
demonstrate this, analytical calculations based on Markov reliability model are
used. It is also shown how the availability parameters can be affected by the
operating environment into which the fault tolerant system is implemented. The
principles of generating sequence of FT architectures with different level of
diagnostic are presented.",
  address="IEEE Computer Society",
  booktitle="12th EUROMICRO Conference on Digital System Design DSD 2009",
  chapter="30207",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2009",
  month="may",
  pages="108--116",
  publisher="IEEE Computer Society",
  type="conference paper"
}