Detail publikace

High Availability Fault Tolerant Architectures Implemented into FPGAs

STRAKA, M. KOTÁSEK, Z.

Originální název

High Availability Fault Tolerant Architectures Implemented into FPGAs

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

In the paper, the methodology of fault tolerant systems design based on FPGA are presented. The architectures are based both on duplex and TMR systems to which fault detection capabilities are added, the use of on-line checkers for this purpose is demonstrated. It is described how reliability and availability parameters in TMR and duplex structures with checkers can be increased. To demonstrate this, analytical calculations based on Markov reliability model are used. It is also shown how the availability parameters can be affected by the operating environment into which the fault tolerant system is implemented. The principles of generating sequence of FT architectures with different level of diagnostic are presented.

Klíčová slova

TMR, availability, Markov reliability model, FPGA, fault tolerant systems, checker

Autoři

STRAKA, M.; KOTÁSEK, Z.

Rok RIV

2009

Vydáno

5. 5. 2009

Nakladatel

IEEE Computer Society

Místo

Patras

ISBN

978-0-7695-3782-5

Kniha

12th EUROMICRO Conference on Digital System Design DSD 2009

Strany od

108

Strany do

116

Strany počet

8

BibTex

@inproceedings{BUT30207,
  author="Martin {Straka} and Zdeněk {Kotásek}",
  title="High Availability Fault Tolerant Architectures Implemented into FPGAs",
  booktitle="12th EUROMICRO Conference on Digital System Design DSD 2009",
  year="2009",
  pages="108--116",
  publisher="IEEE Computer Society",
  address="Patras",
  isbn="978-0-7695-3782-5"
}