Detail publikace

Design -Time Configurable Processor Basic Structure

ADAMEC, F. FRÝZA, T.

Originální název

Design -Time Configurable Processor Basic Structure

Anglický název

Design -Time Configurable Processor Basic Structure

Jazyk

en

Originální abstrakt

In this work the concept of design time configurable processor is introduced. The basic architecture of designed processor core and the basic instruction set. There are described minimal core configuration (integer core) and its programming model. Processor tightly coupled peripheral like a Cache, Memory Management Unit, Protection Unit and Segment Unit are introduced. There are as well the proposed blocks for power management and power save modes. In the conclusion, the comparison between other similar designs is outlined. There is summarized actual state of work and future work is proposed as well.

Anglický abstrakt

In this work the concept of design time configurable processor is introduced. The basic architecture of designed processor core and the basic instruction set. There are described minimal core configuration (integer core) and its programming model. Processor tightly coupled peripheral like a Cache, Memory Management Unit, Protection Unit and Segment Unit are introduced. There are as well the proposed blocks for power management and power save modes. In the conclusion, the comparison between other similar designs is outlined. There is summarized actual state of work and future work is proposed as well.

Dokumenty

BibTex


@inproceedings{BUT29683,
  author="Filip {Adamec} and Tomáš {Frýza}",
  title="Design -Time Configurable Processor Basic Structure",
  annote="In this work the concept of design time configurable processor is introduced. The basic architecture of designed processor core and the basic instruction set. There are described minimal core configuration (integer core) and its programming model. Processor tightly coupled peripheral like a Cache, Memory Management Unit, Protection Unit and Segment Unit are introduced. There are as well the proposed blocks for power management and power save modes. In the conclusion, the comparison between other similar designs is outlined. There is summarized actual state of work and future work is proposed as well.",
  address="Vienna University of Technology, Austria",
  booktitle="Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.",
  chapter="29683",
  howpublished="electronic, physical medium",
  institution="Vienna University of Technology, Austria",
  year="2010",
  month="april",
  pages="119--120",
  publisher="Vienna University of Technology, Austria",
  type="conference paper"
}