Detail publikace

Test Controller Synthesis Constrained by Circuit Testability Analysis

Originální název

Test Controller Synthesis Constrained by Circuit Testability Analysis

Anglický název

Test Controller Synthesis Constrained by Circuit Testability Analysis

Jazyk

en

Originální abstrakt

In the paper, a method for test controller synthesis based on testability analysis results is presented. The proposed method enables to create a Finite State Machine with output, which can control all enable, address and clock inputs of elements in the circuit during the test application process. Proposed testability analysis method is efficient for RT level pipelined data-path circuit. Close coupling of testability analysis and test controller synthesis saves the test cost in terms of area overhead, test time and fault coverage. All processes are described formally.

Anglický abstrakt

In the paper, a method for test controller synthesis based on testability analysis results is presented. The proposed method enables to create a Finite State Machine with output, which can control all enable, address and clock inputs of elements in the circuit during the test application process. Proposed testability analysis method is efficient for RT level pipelined data-path circuit. Close coupling of testability analysis and test controller synthesis saves the test cost in terms of area overhead, test time and fault coverage. All processes are described formally.

BibTex


@inproceedings{BUT28840,
  author="Richard {Růžička} and Josef {Strnadel}",
  title="Test Controller Synthesis Constrained by Circuit Testability Analysis",
  annote="In the paper, a method for test controller synthesis based on testability
analysis results is presented. The proposed method enables to create a Finite
State Machine with output, which can control all enable, address and clock inputs
of elements in the circuit during the test application process. Proposed
testability analysis method is efficient for RT level pipelined data-path
circuit. Close coupling of testability analysis and test controller synthesis
saves the test cost in terms of area overhead, test time and fault coverage. All
processes are described formally.",
  address="IEEE Computer Society Press",
  booktitle="Proceedings of 10th Euromicro Conference on Digital System Design, Architectures, Methods and Tools",
  chapter="28840",
  howpublished="print",
  institution="IEEE Computer Society Press",
  year="2007",
  month="august",
  pages="626--633",
  publisher="IEEE Computer Society Press",
  type="conference paper"
}