Detail publikace

VHDL Design of Educational, Modern and Open-Architecture CPU

Originální název

VHDL Design of Educational, Modern and Open-Architecture CPU

Anglický název

VHDL Design of Educational, Modern and Open-Architecture CPU

Jazyk

en

Originální abstrakt

The paper deals with design of a modern, open-architecture CPU utilizable for educational purposes. It is expected that use of the CPU in the educational process will greatly contribute to deeper understanding of key-topics taught in the area of modern architectures. Our CPU is based on the Von-Neumann architecture, equipped with a five-stage pipeline, cache memory unit and simple branch prediction unit. The architecture is designed in VHDL including set of 16 instructions. Rich variety of educative tasks can be performed by means of the CPU. It has been both successfully simulated in ModelSim and synthesized in Precision RTL Synthesis in order to be implemented in FPGA and utilized in practice as a real working CPU.

Anglický abstrakt

The paper deals with design of a modern, open-architecture CPU utilizable for educational purposes. It is expected that use of the CPU in the educational process will greatly contribute to deeper understanding of key-topics taught in the area of modern architectures. Our CPU is based on the Von-Neumann architecture, equipped with a five-stage pipeline, cache memory unit and simple branch prediction unit. The architecture is designed in VHDL including set of 16 instructions. Rich variety of educative tasks can be performed by means of the CPU. It has been both successfully simulated in ModelSim and synthesized in Precision RTL Synthesis in order to be implemented in FPGA and utilized in practice as a real working CPU.

BibTex 


@inproceedings{BUT28605,
  author="Martin {Straka}",
  title="VHDL Design of Educational, Modern and Open-Architecture CPU",
  annote="The paper deals with design of a modern, open-architecture CPU utilizable for
educational

purposes. It is expected that use of the CPU in the educational process will
greatly contribute

to deeper understanding of key-topics taught in the area of modern architectures.
Our

CPU is based on the Von-Neumann architecture, equipped with a five-stage
pipeline, cache

memory unit and simple branch prediction unit. The architecture is designed in
VHDL including

set of 16 instructions. Rich variety of educative tasks can be performed by
means

of the CPU. It has been both successfully simulated in ModelSim and synthesized
in Precision

RTL Synthesis in order to be implemented in FPGA and utilized in practice as a
real

working CPU.",
  address="Brno University of Technology",
  booktitle="Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4",
  chapter="28605",
  howpublished="print",
  institution="Brno University of Technology",
  year="2007",
  month="may",
  pages="457--461",
  publisher="Brno University of Technology",
  type="conference paper"
}