Detail publikace

Digital Systems Architectures Based on On-line Checkers

STRAKA, M. KOTÁSEK, Z. WINTER, J.

Originální název

Digital Systems Architectures Based on On-line Checkers

Anglický název

Digital Systems Architectures Based on On-line Checkers

Jazyk

en

Originální abstrakt

In this paper, we present a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of communication protocols, counters, decoders, registers, comparators, etc. It is also demonstrated how a checker for more complex structures can be developed. We describe the possibilities of utilizing this approach in the design of Fault Tolerant Systems (FTS). Experimental results in terms of FPGA resources needed to synthesize different types of checkers are presented.

Anglický abstrakt

In this paper, we present a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of communication protocols, counters, decoders, registers, comparators, etc. It is also demonstrated how a checker for more complex structures can be developed. We describe the possibilities of utilizing this approach in the design of Fault Tolerant Systems (FTS). Experimental results in terms of FPGA resources needed to synthesize different types of checkers are presented.

Dokumenty

BibTex


@inproceedings{BUT27769,
  author="Martin {Straka} and Zdeněk {Kotásek} and Jan {Winter}",
  title="Digital Systems Architectures Based on On-line Checkers",
  annote="In this paper, we present a methodology for generating
VHDL descriptions of hardware checkers is presented. It is
shown how the methodology can be used to generate on-line
checkers of communication protocols, counters, decoders,
registers, comparators, etc. It is also demonstrated how a
checker for more complex structures can be developed. We
describe the possibilities of utilizing this approach in the design
of Fault Tolerant Systems (FTS). Experimental results
in terms of FPGA resources needed to synthesize different
types of checkers are presented.",
  address="IEEE Computer Society",
  booktitle="11th EUROMICRO Conference on Digital System Design DSD 2008",
  chapter="27769",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2008",
  month="may",
  pages="81--87",
  publisher="IEEE Computer Society",
  type="conference paper"
}