Detail publikace

Digital Systems Architectures Based on On-line Checkers

STRAKA, M. KOTÁSEK, Z. WINTER, J.

Originální název

Digital Systems Architectures Based on On-line Checkers

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

In this paper, we present a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of communication protocols, counters, decoders, registers, comparators, etc. It is also demonstrated how a checker for more complex structures can be developed. We describe the possibilities of utilizing this approach in the design of Fault Tolerant Systems (FTS). Experimental results in terms of FPGA resources needed to synthesize different types of checkers are presented.

Klíčová slova

Fault Tolerant Systems, simple circuit, checker, FPGA, on-line testing, protocols

Autoři

STRAKA, M.; KOTÁSEK, Z.; WINTER, J.

Rok RIV

2008

Vydáno

13. 5. 2008

Nakladatel

IEEE Computer Society

Místo

Parma

ISBN

978-0-7695-3277-6

Kniha

11th EUROMICRO Conference on Digital System Design DSD 2008

Strany od

81

Strany do

87

Strany počet

8

URL

https://www.fit.vut.cz/research/publication/8621/

BibTex

@inproceedings{BUT27769,
  author="Martin {Straka} and Zdeněk {Kotásek} and Jan {Winter}",
  title="Digital Systems Architectures Based on On-line Checkers",
  booktitle="11th EUROMICRO Conference on Digital System Design DSD 2008",
  year="2008",
  pages="81--87",
  publisher="IEEE Computer Society",
  address="Parma",
  isbn="978-0-7695-3277-6",
  url="https://www.fit.vut.cz/research/publication/8621/"
}