Detail publikace

Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration

STAREČEK, L. SEKANINA, L. KOTÁSEK, Z.

Originální název

Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration

Anglický název

Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration

Jazyk

en

Originální abstrakt

In this paper, a new concept which allows the reduction of test vectors volume is presented. The concept is based on reconfiguration of some gates of circuit under test. Instead of testing the original circuit, a circuit which has the same topology (but some of its gate functions are reconfigured) is actually tested. Two possible implementations of the reconfiguration are investigated. Preliminary experiments indicate that test length can be reduced to approx. 70% of its initial value while the increase in transistors is moderate.

Anglický abstrakt

In this paper, a new concept which allows the reduction of test vectors volume is presented. The concept is based on reconfiguration of some gates of circuit under test. Instead of testing the original circuit, a circuit which has the same topology (but some of its gate functions are reconfigured) is actually tested. Two possible implementations of the reconfiguration are investigated. Preliminary experiments indicate that test length can be reduced to approx. 70% of its initial value while the increase in transistors is moderate.

Dokumenty

BibTex 


@inproceedings{BUT27766,
  author="Lukáš {Stareček} and Lukáš {Sekanina} and Zdeněk {Kotásek}",
  title="Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration",
  annote="In this paper, a new concept which allows the reduction of test vectors volume is
presented. The concept is based on reconfiguration of some gates of circuit under
test. Instead of testing the original circuit, a circuit which has the same
topology (but some of its gate functions are reconfigured) is actually tested.
Two possible implementations of the reconfiguration are investigated. Preliminary
experiments indicate that test length can be reduced to approx. 70% of its
initial value while the increase in transistors is moderate.",
  address="IEEE Computer Society",
  booktitle="Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop",
  chapter="27766",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2008",
  month="april",
  pages="255--258",
  publisher="IEEE Computer Society",
  type="conference paper"
}