Detail publikace

High Level Abstraction Language as an Alternative to Embeded Processors for Internet Packet Processing in FPGA

DEDEK, T. MAREK, T. MARTÍNEK, T.

Originální název

High Level Abstraction Language as an Alternative to Embeded Processors for Internet Packet Processing in FPGA

Anglický název

High Level Abstraction Language as an Alternative to Embeded Processors for Internet Packet Processing in FPGA

Jazyk

en

Originální abstrakt

In this paper, we investigate three different realizations of the same block from different points of view. The mentioned different realizations include two realizations with embedded processors (custom 16-bit RISC processor and general soft-core processor) and the third realization uses Handel-C as an example of synthesisable high-level abstraction languages. The results show that development time of complete solution (HW and SW) is approximately the same for the Handel-C design and the design with soft-core processor; the development time of the Custom 16-bit RISC processor is about five times higher. Moreover, the throughput of the Handel-C design measured in the number of bits processed in one second is the highest. The obtained frequency and occupied area of the Handel-C design depends on the complexity of the used program. However, results are comparable or even better than results of the embedded processors.

Anglický abstrakt

In this paper, we investigate three different realizations of the same block from different points of view. The mentioned different realizations include two realizations with embedded processors (custom 16-bit RISC processor and general soft-core processor) and the third realization uses Handel-C as an example of synthesisable high-level abstraction languages. The results show that development time of complete solution (HW and SW) is approximately the same for the Handel-C design and the design with soft-core processor; the development time of the Custom 16-bit RISC processor is about five times higher. Moreover, the throughput of the Handel-C design measured in the number of bits processed in one second is the highest. The obtained frequency and occupied area of the Handel-C design depends on the complexity of the used program. However, results are comparable or even better than results of the embedded processors.

Dokumenty

BibTex


@inproceedings{BUT26060,
  author="Tomáš {Dedek} and Tomáš {Marek} and Tomáš {Martínek}",
  title="High Level Abstraction Language as an Alternative to Embeded Processors for Internet Packet Processing in FPGA",
  annote="In this paper, we investigate three different realizations
of the same block from different points of view. The mentioned
different realizations include two realizations with
embedded processors (custom 16-bit RISC processor and
general soft-core processor) and the third realization uses
Handel-C as an example of synthesisable high-level abstraction
languages.
The results show that development time of complete
solution (HW and SW) is approximately the same for the
Handel-C design and the design with soft-core processor;
the development time of the Custom 16-bit RISC processor
is about five times higher. Moreover, the throughput of the
Handel-C design measured in the number of bits processed
in one second is the highest. The obtained frequency and
occupied area of the Handel-C design depends on the complexity
of the used program. However, results are comparable
or even better than results of the embedded processors.",
  address="IEEE Computer Society",
  booktitle="2007 International Conference on Field Programmable Logic and Applications",
  chapter="26060",
  doi="10.1109/FPL.2007.4380737",
  howpublished="online",
  institution="IEEE Computer Society",
  year="2007",
  month="september",
  pages="648--651",
  publisher="IEEE Computer Society",
  type="conference paper"
}