Detail publikace

RT Level Test Optimization for Low Power Consumption

ŠKARVADA, J.

Originální název

RT Level Test Optimization for Low Power Consumption

Anglický název

RT Level Test Optimization for Low Power Consumption

Jazyk

en

Originální abstrakt

The paper deals with low power consumption test optimization for register transfer level (RTL) circuits. A model of circuit under test (CUT), based on the theory of sets and relations is defined. In the model, the power consumption is seen as a parameter depending on circuit structure and input data used for the test. Optimization method to reduce power consumption during test application, is presented.

Anglický abstrakt

The paper deals with low power consumption test optimization for register transfer level (RTL) circuits. A model of circuit under test (CUT), based on the theory of sets and relations is defined. In the model, the power consumption is seen as a parameter depending on circuit structure and input data used for the test. Optimization method to reduce power consumption during test application, is presented.

Dokumenty

BibTex 


@inproceedings{BUT25354,
  author="Jaroslav {Škarvada}",
  title="RT Level Test Optimization for Low Power Consumption",
  annote="The paper deals with low power consumption test optimization for register
transfer level (RTL) circuits. A model of circuit under test (CUT), based on the
theory of sets and relations is defined. In the model, the power consumption is
seen as a parameter depending on circuit structure and input data used for the
test. Optimization method to reduce power consumption during test application, is
presented.",
  address="Ing. Zdeněk Novotný, CSc.",
  booktitle="MEMICS proceedings 2007",
  chapter="25354",
  howpublished="print",
  institution="Ing. Zdeněk Novotný, CSc.",
  year="2007",
  month="october",
  pages="185--192",
  publisher="Ing. Zdeněk Novotný, CSc.",
  type="conference paper"
}