Detail publikace

Simulation model of Digital Clock and Data Recovery for Strongly Disturbed Signals

KUBÍČEK, M.

Originální název

Simulation model of Digital Clock and Data Recovery for Strongly Disturbed Signals

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

The paper describes VHDL-AMS simulation model of a digital link (with a signal source) together with "software" clock and data recovery module [1] and common recovery circuit incorporating a PLL. Performance of both methods is compared and discussed. Models were created to help to improve the software recovery method. All simulations were performed in the Mentor Graphic's SystemVision 4.4 environment using VHDL-AMS [2] models of signal source, data path and recovery circuits. The soft-ware recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design.

Klíčová slova

Simulation, VHDL-AMS, Clock and data recovery, SystemVision

Autoři

KUBÍČEK, M.

Rok RIV

2007

Vydáno

1. 1. 2007

Nakladatel

Ing. Zdeněk Novotný CSc., Ondráčková 105, Brno

Místo

Vysoké učení technické v Brně

ISBN

978-80-214-3410-3

Kniha

Proceedings of the 13th Conference Student EEICT 2007

Strany od

266

Strany do

270

Strany počet

5

BibTex

@inproceedings{BUT22611,
  author="Michal {Kubíček}",
  title="Simulation model of Digital Clock and Data Recovery for Strongly Disturbed Signals",
  booktitle="Proceedings of the 13th Conference Student EEICT 2007",
  year="2007",
  pages="266--270",
  publisher="Ing. Zdeněk Novotný CSc., Ondráčková 105, Brno",
  address="Vysoké učení technické v Brně",
  isbn="978-80-214-3410-3"
}