Detail publikace

10G BIT ETHERNET PHY IMPLEMENTATION IN FPGA BASED SYSTEMS

BRADÁČ, Z., VALACH, S.

Originální název

10G BIT ETHERNET PHY IMPLEMENTATION IN FPGA BASED SYSTEMS

Anglický název

10G BIT ETHERNET PHY IMPLEMENTATION IN FPGA BASED SYSTEMS

Jazyk

en

Originální abstrakt

The present electronic industry achieves unusual expansion of communication technology based on high-speed serial interfaces. It is due to need higher bandwidth and performance, lower size, power consumption and device price. The article will be focused on a different approaches how to implement 10 GigaBit Ethernet physical layer in the FPGA based structures.

Anglický abstrakt

The present electronic industry achieves unusual expansion of communication technology based on high-speed serial interfaces. It is due to need higher bandwidth and performance, lower size, power consumption and device price. The article will be focused on a different approaches how to implement 10 GigaBit Ethernet physical layer in the FPGA based structures.

Dokumenty

BibTex 


@inproceedings{BUT19451,
  author="Zdeněk {Bradáč} and Soběslav {Valach}",
  title="10G BIT ETHERNET PHY IMPLEMENTATION IN FPGA BASED SYSTEMS",
  annote="The present electronic industry achieves unusual expansion of communication
technology based on high-speed serial interfaces. It is due to need higher bandwidth and
performance, lower size, power consumption and device price. The article will be focused
on a different approaches how to implement 10 GigaBit Ethernet physical layer in the
FPGA based structures.",
  address="VUT Brno",
  booktitle="Proceedings of IFAC WORKSHOP on Programmable Devices and Embedded Systems PDeS2003",
  chapter="19451",
  institution="VUT Brno",
  year="2006",
  month="february",
  pages="427",
  publisher="VUT Brno",
  type="conference paper"
}