Detail publikace

On the Petri Net Based Test Scheduling

RŮŽIČKA, R.

Originální název

On the Petri Net Based Test Scheduling

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

This paper discusses some problems with test scheduling optimization of register transfer level (RTL) digital circuit design. The Petri net model, previously proposed for testability verification purposes is now used as a base of C/E system which models test application process. To schedule application of test patterns to elements of a circuit under test, possibility of concurrency must be considered firstly. Parallelism during test application process can significantly reduce time of testing. Another advantage of the approach is that all methods are described formally and are proved.

Klíčová slova

RTL digital circuit testability, test scheduling optimization

Autoři

RŮŽIČKA, R.

Rok RIV

2005

Vydáno

30. 8. 2005

Nakladatel

Johannes Kepler University Linz

Místo

Linz

ISBN

3-902457-09-0

Kniha

Proceedings of the Work in Progress Session at Euromicro SEAA/DSD 2005

Strany od

18

Strany do

19

Strany počet

2

BibTex

@inproceedings{BUT18034,
  author="Richard {Růžička}",
  title="On the Petri Net Based Test Scheduling",
  booktitle="Proceedings of the Work in Progress Session at Euromicro SEAA/DSD 2005",
  year="2005",
  pages="18--19",
  publisher="Johannes Kepler University Linz",
  address="Linz",
  isbn="3-902457-09-0"
}