Detail publikace

Design of the Special Fast Reconfigurable Chip Using Common FPGA

SEKANINA, L., RŮŽIČKA, R.

Originální název

Design of the Special Fast Reconfigurable Chip Using Common FPGA

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

Some applications require chips with fast partial reconfiguration. These requirements are traditionally satisfied by a special chip design, but it is usually a very expensive solution. This paper describes a new approach. Special fast partially reconfigurable chip is implemented with a common FPGA. The format of the configuration bit stream is suggested and optimized according to the given task. Result chip offers many good properties, but some problems with scalability can appear.

Klíčová slova

reconfigurable circuits, evolvable hardware

Autoři

SEKANINA, L., RŮŽIČKA, R.

Vydáno

1. 1. 2000

Nakladatel

unknown

Místo

Smolenice

ISBN

80-968320-3-4

Kniha

Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000

Strany od

161

Strany do

168

Strany počet

8

URL

http://www.fit.vutbr.cz/~sekanina/publ/ddecs00/rechip.pdf

BibTex

@inproceedings{BUT17637,
  author="Lukáš {Sekanina} and Richard {Růžička}",
  title="Design of the Special Fast Reconfigurable Chip Using Common FPGA",
  booktitle="Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000",
  year="2000",
  pages="161--168",
  publisher="unknown",
  address="Smolenice",
  isbn="80-968320-3-4",
  url="http://www.fit.vutbr.cz/~sekanina/publ/ddecs00/rechip.pdf"
}