Detail publikace

On Routine Implementation of Virtual Evolvable Devices Using COMBO6

SEKANINA, L., FRIEDL, Š.

Originální název

On Routine Implementation of Virtual Evolvable Devices Using COMBO6

Anglický název

On Routine Implementation of Virtual Evolvable Devices Using COMBO6

Jazyk

en

Originální abstrakt

This paper introduces an approach showing that a complete implementation of a digital evolvable hardware system can automatically be created from a high-level specification.
The approach generates the implementation of a virtual reconfigurable circuit and  evolutionary algorithm independently of a target platform, i.e. as a soft IP core. The method is evaluated on the development of two high-performance evolvable systems that are utilized for fast evolutionary design of small combinational circuits, such as 3x3-bit multipliers. The COMBO6 card is employed for these experiments.

Anglický abstrakt

This paper introduces an approach showing that a complete implementation of a digital evolvable hardware system can automatically be created from a high-level specification.
The approach generates the implementation of a virtual reconfigurable circuit and  evolutionary algorithm independently of a target platform, i.e. as a soft IP core. The method is evaluated on the development of two high-performance evolvable systems that are utilized for fast evolutionary design of small combinational circuits, such as 3x3-bit multipliers. The COMBO6 card is employed for these experiments.

Dokumenty

BibTex 


@inproceedings{BUT17342,
  author="Lukáš {Sekanina} and Štěpán {Friedl}",
  title="On Routine Implementation of Virtual Evolvable Devices Using COMBO6",
  annote="This paper introduces an approach showing that a complete implementation of a digital evolvable hardware system can automatically be created from a high-level specification. 
The approach generates the implementation of a virtual reconfigurable circuit and  evolutionary algorithm independently of a target platform, i.e. as a soft IP core. The method is evaluated on the development of two high-performance evolvable systems that are utilized for fast evolutionary design of small combinational circuits, such as 3x3-bit multipliers. The COMBO6 card is employed for these experiments.
",
  address="IEEE Computer Society Press",
  booktitle="Proc. of the 2004 NASA/DoD Conference on Evolvable Hardware",
  chapter="17342",
  institution="IEEE Computer Society Press",
  year="2004",
  month="june",
  pages="63--70",
  publisher="IEEE Computer Society Press",
  type="conference paper"
}