Detail publikace

Hardware cryptographic module for FPGA with dynamic hash functions routing

KERNDL, M. ŠTEFFAN, P.

Originální název

Hardware cryptographic module for FPGA with dynamic hash functions routing

Anglický název

Hardware cryptographic module for FPGA with dynamic hash functions routing

Jazyk

en

Originální abstrakt

This paper deals with design of hardware cryptographic module for System-on-Chip that can be simulated on FPGA. The main function of this module is dynamic routing of SHA-3 hash function candidates that are commonly used s X11 hash algorithm. Proposed design was verified and evaluated using Virtual Platform methodology and aims to be an example of development of system based on Virtual Platform. Designed architecture can be deployed on FPGA or real hardware platform. This hardware can be used in Internet-of-Things or another related applications.

Anglický abstrakt

This paper deals with design of hardware cryptographic module for System-on-Chip that can be simulated on FPGA. The main function of this module is dynamic routing of SHA-3 hash function candidates that are commonly used s X11 hash algorithm. Proposed design was verified and evaluated using Virtual Platform methodology and aims to be an example of development of system based on Virtual Platform. Designed architecture can be deployed on FPGA or real hardware platform. This hardware can be used in Internet-of-Things or another related applications.

Dokumenty

BibTex


@inproceedings{BUT158569,
  author="Michal {Kerndl} and Pavel {Šteffan}",
  title="Hardware cryptographic module for FPGA with dynamic hash functions routing",
  annote="This paper deals with design of hardware cryptographic module for System-on-Chip that can be simulated on FPGA. The main function of this module is dynamic routing of SHA-3 hash function candidates that are commonly used s X11 hash algorithm. Proposed design was verified and evaluated using Virtual Platform methodology and aims to be an example of development of system based on Virtual Platform. Designed architecture can be deployed on FPGA or real hardware platform. This hardware can be used in Internet-of-Things or another related applications.",
  booktitle="Proceedings of IEEE Student Branch Conference Mikulov 2019",
  chapter="158569",
  howpublished="print",
  year="2019",
  month="september",
  pages="39--41",
  type="conference paper"
}