Detail publikace

All-Pass Time Delay Circuit Magnitude Response Optimization Using Fractional-Order Capacitor

Originální název

All-Pass Time Delay Circuit Magnitude Response Optimization Using Fractional-Order Capacitor

Anglický název

All-Pass Time Delay Circuit Magnitude Response Optimization Using Fractional-Order Capacitor

Jazyk

en

Originální abstrakt

Paper presents the integer- and fractional-order cases of a voltage-mode all-pass time delay circuit, or more frequently called as all-pass filter, employing a single negative-type current-controlled current inverting transconductance amplifier and a floating capacitor. Utilization of a fractional-order capacitor (FoC) C_0.96 with 12 pFsec-0.04 value for magnitude response optimization of the filter is investigated. FoC was emulated via 4th-order Valsa RC network and values optimized using modified least squares quadratic method. In frequency range 1 MHz-1 GHz it shows only +-0.5 degree phase angle deviation and the relative pseudo-capacitance error varies from -1.85% to +0.73%. SPICE simulations are given to prove the theory.

Anglický abstrakt

Paper presents the integer- and fractional-order cases of a voltage-mode all-pass time delay circuit, or more frequently called as all-pass filter, employing a single negative-type current-controlled current inverting transconductance amplifier and a floating capacitor. Utilization of a fractional-order capacitor (FoC) C_0.96 with 12 pFsec-0.04 value for magnitude response optimization of the filter is investigated. FoC was emulated via 4th-order Valsa RC network and values optimized using modified least squares quadratic method. In frequency range 1 MHz-1 GHz it shows only +-0.5 degree phase angle deviation and the relative pseudo-capacitance error varies from -1.85% to +0.73%. SPICE simulations are given to prove the theory.

BibTex


@inproceedings{BUT149105,
  author="Norbert {Herencsár} and Aslihan {Kartci} and Esteban {Tlelo-Cuautle} and Bilgin {Metin} and Oguzhan {Cicekoglu}",
  title="All-Pass Time Delay Circuit Magnitude Response Optimization Using Fractional-Order Capacitor",
  annote="Paper presents the integer- and fractional-order cases of a voltage-mode all-pass time delay circuit, or more frequently called as all-pass filter, employing a single negative-type current-controlled current inverting transconductance amplifier and a floating capacitor. Utilization of a fractional-order capacitor (FoC) C_0.96 with 12 pFsec-0.04 value for magnitude response optimization of the filter is investigated. FoC was emulated via 4th-order Valsa RC network and values optimized using modified least squares quadratic method. In frequency range 1 MHz-1 GHz it shows only +-0.5 degree phase angle deviation and the relative pseudo-capacitance error varies from -1.85% to +0.73%. SPICE simulations are given to prove the theory.",
  booktitle="Proceedings of the 2018 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)",
  chapter="149105",
  howpublished="electronic, physical medium",
  year="2018",
  month="august",
  pages="129--132",
  type="conference paper"
}