Detail publikace

Testable Design Verification Using Petri Nets

RŮŽIČKA, R.

Originální název

Testable Design Verification Using Petri Nets

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

In the paper, a method for formal verification of testable design is presented. As a input, a digital circuit structure at RT level designed using any DfT technique is assumed. Proposed method enables to verify testability of each element or a part of the circuit. Petri Net based model and common methods of Petri Net analysis are utilised. On the model, it is possible to prove, if a circuit element or a part of the circuit under test can be tested by a selected way - if paths, chosen for diagnostic data transport, are passable or not and if not, for what reason.

Klíčová slova

Testability Analysis, Testability Verification, Petri Nets, I path, RTL Digital Circuits

Autoři

RŮŽIČKA, R.

Rok RIV

2003

Vydáno

1. 9. 2003

Nakladatel

IEEE Computer Society Press

Místo

Los Alamitos, CA

ISBN

0-7695-2003-0

Kniha

Proceedings of Euromicro Symposium on Digital System Design 2003

Strany od

304

Strany do

311

Strany počet

8

BibTex

@inproceedings{BUT14194,
  author="Richard {Růžička}",
  title="Testable Design Verification Using Petri Nets",
  booktitle="Proceedings of Euromicro Symposium on Digital System Design 2003",
  year="2003",
  pages="304--311",
  publisher="IEEE Computer Society Press",
  address="Los Alamitos, CA",
  isbn="0-7695-2003-0"
}