Detail publikace

Testing PCBs Based on Boundary Scan

KOTÁSEK, Z., TUPEC, P., URBIŠ, H.

Originální název

Testing PCBs Based on Boundary Scan

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

The paper describes a practical approach to testing PCBs with Xilinx FPGAs. The approach is based on a PCB netlist analysis, which is revealing the existing connections on the PCB through the Boundary Scan chain and comparing the two results. It is also supposed that the developed software tools will be used for debugging PCBs with Xilinx FPGAs. The goal of the research activities is to develop an easy to use an efficient and user- friendly software tools.

Klíčová slova

Boundary Scan, PCB, FPGA

Autoři

KOTÁSEK, Z., TUPEC, P., URBIŠ, H.

Rok RIV

2003

Vydáno

26. 5. 2003

Nakladatel

The University of Technology Košice

Místo

Košice

ISBN

80-7099-509-2

Kniha

Proceedings of International Carpathian Control Conference

Strany od

119

Strany do

122

Strany počet

4

BibTex

@inproceedings{BUT14165,
  author="Zdeněk {Kotásek} and Pavel {Tupec} and Hynek {Urbiš}",
  title="Testing PCBs Based on Boundary Scan",
  booktitle="Proceedings of International Carpathian Control Conference",
  year="2003",
  pages="119--122",
  publisher="The University of Technology Košice",
  address="Košice",
  isbn="80-7099-509-2"
}