Detail publikace

A High Speed Middle Accuracy 9-bit SAR-ADC in 0.35-um CMOS for Sensor Application in Automotive Industry

Originální název

A High Speed Middle Accuracy 9-bit SAR-ADC in 0.35-um CMOS for Sensor Application in Automotive Industry

Anglický název

A High Speed Middle Accuracy 9-bit SAR-ADC in 0.35-um CMOS for Sensor Application in Automotive Industry

Jazyk

en

Originální abstrakt

This paper describes a 9-bit Successive Approximation Register Analog to Digital Converter (SAR-ADC) design in CMOS technology, particularly I4T, 0.35 um, 45 V, used in automotive industry for sensor application. There are the individual analogue components of the SAR-DAC descibed in this paper: the Comparator, the R-2R Digital to Analog Converter (DAC) and the Operational Amplifier (OPA). The functionality and the parameters of the SAR-ADC were verified in analog design environment Cadence Virtuoso. The parameters of the designed SAR-ADC are published in this paper.

Anglický abstrakt

This paper describes a 9-bit Successive Approximation Register Analog to Digital Converter (SAR-ADC) design in CMOS technology, particularly I4T, 0.35 um, 45 V, used in automotive industry for sensor application. There are the individual analogue components of the SAR-DAC descibed in this paper: the Comparator, the R-2R Digital to Analog Converter (DAC) and the Operational Amplifier (OPA). The functionality and the parameters of the SAR-ADC were verified in analog design environment Cadence Virtuoso. The parameters of the designed SAR-ADC are published in this paper.

BibTex


@inproceedings{BUT137880,
  author="Zuzana {Bečková} and Jan {Jeřábek}",
  title="A High Speed Middle Accuracy 9-bit SAR-ADC in 0.35-um CMOS for Sensor Application in Automotive Industry",
  annote="This paper describes a 9-bit Successive Approximation Register Analog to Digital Converter (SAR-ADC) design
in CMOS technology, particularly I4T, 0.35 um, 45 V, used in automotive industry for sensor application. There are the individual analogue components of the SAR-DAC descibed in this paper: the Comparator, the R-2R Digital to Analog Converter (DAC) and the Operational Amplifier (OPA). The functionality and the parameters of the SAR-ADC were verified in analog design environment Cadence Virtuoso. The parameters of the designed SAR-ADC are published in this paper.",
  booktitle="Proceedings of the 40th International Conference on Telecommunications and Signal Processing (TSP 2017)",
  chapter="137880",
  doi="10.1109/TSP.2017.8075997",
  howpublished="electronic, physical medium",
  year="2017",
  month="july",
  pages="325--239",
  type="conference paper"
}